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786a4ea82e
This commit was generated mechanically by coccinelle from the following semantic patch: @@ expression val; @@ - (ffs(val) - 1) + ctz32(val) The call sites have been audited to ensure the ffs(0) - 1 == -1 case never occurs (due to input validation, asserts, etc). Therefore we don't need to worry about the fact that ctz32(0) == 32. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-5-git-send-email-stefanha@redhat.com Signed-off-by: Kevin Wolf <kwolf@redhat.com>
46 lines
1.3 KiB
C
46 lines
1.3 KiB
C
#include "hw/pci/slotid_cap.h"
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#include "hw/pci/pci.h"
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#include "qemu/error-report.h"
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#define SLOTID_CAP_LENGTH 4
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#define SLOTID_NSLOTS_SHIFT ctz32(PCI_SID_ESR_NSLOTS)
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int slotid_cap_init(PCIDevice *d, int nslots,
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uint8_t chassis,
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unsigned offset)
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{
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int cap;
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if (!chassis) {
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error_report("Bridge chassis not specified. Each bridge is required "
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"to be assigned a unique chassis id > 0.");
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return -EINVAL;
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}
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if (nslots < 0 || nslots > (PCI_SID_ESR_NSLOTS >> SLOTID_NSLOTS_SHIFT)) {
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/* TODO: error report? */
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return -EINVAL;
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}
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cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, SLOTID_CAP_LENGTH);
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if (cap < 0) {
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return cap;
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}
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/* We make each chassis unique, this way each bridge is First in Chassis */
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d->config[cap + PCI_SID_ESR] = PCI_SID_ESR_FIC |
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(nslots << SLOTID_NSLOTS_SHIFT);
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d->cmask[cap + PCI_SID_ESR] = 0xff;
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d->config[cap + PCI_SID_CHASSIS_NR] = chassis;
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/* Note: Chassis number register is non-volatile,
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so we don't reset it. */
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/* TODO: store in eeprom? */
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d->wmask[cap + PCI_SID_CHASSIS_NR] = 0xff;
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d->cap_present |= QEMU_PCI_CAP_SLOTID;
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return 0;
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}
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void slotid_cap_cleanup(PCIDevice *d)
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{
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/* TODO: cleanup config space? */
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d->cap_present &= ~QEMU_PCI_CAP_SLOTID;
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}
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