Emilio G. Cota ccf08e40bf target/riscv: call gen_goto_tb on DISAS_TOO_MANY ... Performance impact of this and the previous commits, measured with the very-easy-to-cross-compile rv8-bench: https://github.com/rv8-io/rv8-bench Host: Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz - Key: before: master after1,2,3: the 3 commits in this series (i.e. 3 is this commit) - User-mode: bench before after1 after2 after3 final speedup --------------------------------------------------------- aes 1.12s 1.12s 1.10s 1.00s 1.12 bigint 0.78s 0.78s 0.78s 0.78s 1 dhrystone 0.96s 0.97s 0.49s 0.49s 1.9591837 miniz 1.94s 1.94s 1.88s 1.86s 1.0430108 norx 0.51s 0.51s 0.49s 0.48s 1.0625 primes 0.85s 0.85s 0.84s 0.84s 1.0119048 qsort 4.87s 4.88s 1.86s 1.86s 2.6182796 sha512 0.76s 0.77s 0.64s 0.64s 1.1875 (after1 only applies to softmmu, so no surprises here) - Full-system (fedora): bench before after1 after2 after3 final speedup --------------------------------------------------------- aes 2.68s 2.54s 2.60s 2.34s 1.1452991 bigint 1.61s 1.56s 1.55s 1.64s 0.98170732 dhrystone 1.78s 1.67s 1.25s 1.24s 1.4354839 miniz 3.53s 3.35s 3.28s 3.35s 1.0537313 norx 1.13s 1.09s 1.07s 1.06s 1.0660377 primes 15.37s 15.41s 15.20s 15.37s 1 qsort 7.20s 6.71s 3.85s 3.96s 1.8181818 sha512 1.07s 1.04s 0.90s 0.90s 1.1888889 SoftMMU slows things down, so the numbers are less sensitive. Cross-page jumps improve things a little bit, though. Note that I'm not showing here averages, just results from a single run, so with primes there isn't much to worry about. Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2018-09-05 09:58:38 -07:00
..
cpu_bits.h	RISC-V: Improve page table walker spec compliance	2018-09-04 13:19:23 -07:00
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
cpu.c	target/riscv: Honor CPU_DUMP_FPU	2018-05-18 14:52:38 -07:00
cpu.h	RISC-V: Update address bits to support sv39 and sv48	2018-09-04 13:19:12 -07:00
fpu_helper.c	target/riscv: Remove floatX_maybe_silence_nan from conversions	2018-05-17 15:27:15 -07:00
gdbstub.c	RISC-V GDB Stub	2018-03-07 08:30:28 +13:00
helper.c	RISC-V: Simplify riscv_cpu_local_irqs_pending	2018-09-04 13:19:37 -07:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	RISC-V Build Infrastructure	2018-03-07 08:30:28 +13:00
op_helper.c	RISC-V: Add trailing '\n' to qemu_log() calls	2018-06-08 13:15:33 +01:00
pmp.c	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	target/riscv: call gen_goto_tb on DISAS_TOO_MANY	2018-09-05 09:58:38 -07:00