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c759b24fae
Include dependencies from pci core using the correct path. This is required now that it's in the separate directory. Need to check whether they can be minimized, for now, keep the code as is. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
143 lines
5.9 KiB
C
143 lines
5.9 KiB
C
/*
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* pcie.h
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*
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef QEMU_PCIE_H
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#define QEMU_PCIE_H
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#include "hw/hw.h"
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#include "hw/pci/pci_regs.h"
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#include "hw/pci/pcie_regs.h"
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#include "hw/pci/pcie_aer.h"
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typedef enum {
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/* for attention and power indicator */
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PCI_EXP_HP_IND_RESERVED = PCI_EXP_SLTCTL_IND_RESERVED,
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PCI_EXP_HP_IND_ON = PCI_EXP_SLTCTL_IND_ON,
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PCI_EXP_HP_IND_BLINK = PCI_EXP_SLTCTL_IND_BLINK,
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PCI_EXP_HP_IND_OFF = PCI_EXP_SLTCTL_IND_OFF,
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} PCIExpressIndicator;
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typedef enum {
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/* these bits must match the bits in Slot Control/Status registers.
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* PCI_EXP_HP_EV_xxx = PCI_EXP_SLTCTL_xxxE = PCI_EXP_SLTSTA_xxx
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*
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* Not all the bits of slot control register match with the ones of
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* slot status. Not some bits of slot status register is used to
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* show status, not to report event occurrence.
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* So such bits must be masked out when checking the software
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* notification condition.
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*/
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PCI_EXP_HP_EV_ABP = PCI_EXP_SLTCTL_ABPE,
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/* attention button pressed */
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PCI_EXP_HP_EV_PDC = PCI_EXP_SLTCTL_PDCE,
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/* presence detect changed */
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PCI_EXP_HP_EV_CCI = PCI_EXP_SLTCTL_CCIE,
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/* command completed */
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PCI_EXP_HP_EV_SUPPORTED = PCI_EXP_HP_EV_ABP |
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PCI_EXP_HP_EV_PDC |
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PCI_EXP_HP_EV_CCI,
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/* supported event mask */
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/* events not listed aren't supported */
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} PCIExpressHotPlugEvent;
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struct PCIExpressDevice {
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/* Offset of express capability in config space */
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uint8_t exp_cap;
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/* SLOT */
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unsigned int hpev_intx; /* INTx for hot plug event (0-3:INT[A-D]#)
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* default is 0 = INTA#
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* If the chip wants to use other interrupt
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* line, initialize this member with the
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* desired number.
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* If the chip dynamically changes this member,
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* also initialize it when loaded as
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* appropreately.
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*/
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bool hpev_notified; /* Logical AND of conditions for hot plug event.
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Following 6.7.3.4:
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Software Notification of Hot-Plug Events, an interrupt
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is sent whenever the logical and of these conditions
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transitions from false to true. */
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/* AER */
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uint16_t aer_cap;
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PCIEAERLog aer_log;
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unsigned int aer_intx; /* INTx for error reporting
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* default is 0 = INTA#
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* If the chip wants to use other interrupt
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* line, initialize this member with the
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* desired number.
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* If the chip dynamically changes this member,
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* also initialize it when loaded as
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* appropreately.
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*/
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};
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/* PCI express capability helper functions */
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int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port);
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void pcie_cap_exit(PCIDevice *dev);
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uint8_t pcie_cap_get_type(const PCIDevice *dev);
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void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector);
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uint8_t pcie_cap_flags_get_vector(PCIDevice *dev);
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void pcie_cap_deverr_init(PCIDevice *dev);
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void pcie_cap_deverr_reset(PCIDevice *dev);
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void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot);
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void pcie_cap_slot_reset(PCIDevice *dev);
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void pcie_cap_slot_write_config(PCIDevice *dev,
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uint32_t addr, uint32_t val, int len);
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int pcie_cap_slot_post_load(void *opaque, int version_id);
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void pcie_cap_slot_push_attention_button(PCIDevice *dev);
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void pcie_cap_root_init(PCIDevice *dev);
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void pcie_cap_root_reset(PCIDevice *dev);
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void pcie_cap_flr_init(PCIDevice *dev);
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void pcie_cap_flr_write_config(PCIDevice *dev,
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uint32_t addr, uint32_t val, int len);
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void pcie_cap_ari_init(PCIDevice *dev);
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void pcie_cap_ari_reset(PCIDevice *dev);
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bool pcie_cap_is_ari_enabled(const PCIDevice *dev);
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/* PCI express extended capability helper functions */
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uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id);
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void pcie_add_capability(PCIDevice *dev,
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uint16_t cap_id, uint8_t cap_ver,
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uint16_t offset, uint16_t size);
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void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn);
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extern const VMStateDescription vmstate_pcie_device;
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#define VMSTATE_PCIE_DEVICE(_field, _state) { \
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.name = (stringify(_field)), \
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.size = sizeof(PCIDevice), \
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.vmsd = &vmstate_pcie_device, \
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.flags = VMS_STRUCT, \
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.offset = vmstate_offset_value(_state, _field, PCIDevice), \
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}
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#endif /* QEMU_PCIE_H */
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