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d1f711d407
Add the STM32F2xx ADC device. This device randomly generates values on each read. This also includes creating a hw/adc directory. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 3240e660adaf537f55a63ce06096e844aece8cda.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
307 lines
9.0 KiB
C
307 lines
9.0 KiB
C
/*
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* STM32F2XX ADC
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/hw.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "hw/adc/stm32f2xx_adc.h"
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#ifndef STM_ADC_ERR_DEBUG
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#define STM_ADC_ERR_DEBUG 0
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#endif
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#define DB_PRINT_L(lvl, fmt, args...) do { \
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if (STM_ADC_ERR_DEBUG >= lvl) { \
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qemu_log("%s: " fmt, __func__, ## args); \
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} \
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} while (0);
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#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
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static void stm32f2xx_adc_reset(DeviceState *dev)
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{
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STM32F2XXADCState *s = STM32F2XX_ADC(dev);
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s->adc_sr = 0x00000000;
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s->adc_cr1 = 0x00000000;
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s->adc_cr2 = 0x00000000;
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s->adc_smpr1 = 0x00000000;
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s->adc_smpr2 = 0x00000000;
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s->adc_jofr[0] = 0x00000000;
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s->adc_jofr[1] = 0x00000000;
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s->adc_jofr[2] = 0x00000000;
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s->adc_jofr[3] = 0x00000000;
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s->adc_htr = 0x00000FFF;
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s->adc_ltr = 0x00000000;
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s->adc_sqr1 = 0x00000000;
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s->adc_sqr2 = 0x00000000;
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s->adc_sqr3 = 0x00000000;
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s->adc_jsqr = 0x00000000;
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s->adc_jdr[0] = 0x00000000;
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s->adc_jdr[1] = 0x00000000;
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s->adc_jdr[2] = 0x00000000;
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s->adc_jdr[3] = 0x00000000;
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s->adc_dr = 0x00000000;
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}
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static uint32_t stm32f2xx_adc_generate_value(STM32F2XXADCState *s)
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{
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/* Attempts to fake some ADC values */
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s->adc_dr = s->adc_dr + 7;
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switch ((s->adc_cr1 & ADC_CR1_RES) >> 24) {
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case 0:
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/* 12-bit */
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s->adc_dr &= 0xFFF;
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break;
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case 1:
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/* 10-bit */
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s->adc_dr &= 0x3FF;
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break;
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case 2:
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/* 8-bit */
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s->adc_dr &= 0xFF;
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break;
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default:
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/* 6-bit */
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s->adc_dr &= 0x3F;
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}
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if (s->adc_cr2 & ADC_CR2_ALIGN) {
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return (s->adc_dr << 1) & 0xFFF0;
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} else {
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return s->adc_dr;
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}
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}
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static uint64_t stm32f2xx_adc_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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STM32F2XXADCState *s = opaque;
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DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);
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if (addr >= ADC_COMMON_ADDRESS) {
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qemu_log_mask(LOG_UNIMP,
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"%s: ADC Common Register Unsupported\n", __func__);
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}
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switch (addr) {
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case ADC_SR:
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return s->adc_sr;
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case ADC_CR1:
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return s->adc_cr1;
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case ADC_CR2:
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return s->adc_cr2 & 0xFFFFFFF;
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case ADC_SMPR1:
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return s->adc_smpr1;
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case ADC_SMPR2:
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return s->adc_smpr2;
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case ADC_JOFR1:
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case ADC_JOFR2:
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case ADC_JOFR3:
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case ADC_JOFR4:
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qemu_log_mask(LOG_UNIMP, "%s: " \
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"Injection ADC is not implemented, the registers are " \
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"included for compatibility\n", __func__);
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return s->adc_jofr[(addr - ADC_JOFR1) / 4];
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case ADC_HTR:
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return s->adc_htr;
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case ADC_LTR:
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return s->adc_ltr;
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case ADC_SQR1:
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return s->adc_sqr1;
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case ADC_SQR2:
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return s->adc_sqr2;
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case ADC_SQR3:
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return s->adc_sqr3;
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case ADC_JSQR:
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qemu_log_mask(LOG_UNIMP, "%s: " \
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"Injection ADC is not implemented, the registers are " \
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"included for compatibility\n", __func__);
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return s->adc_jsqr;
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case ADC_JDR1:
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case ADC_JDR2:
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case ADC_JDR3:
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case ADC_JDR4:
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qemu_log_mask(LOG_UNIMP, "%s: " \
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"Injection ADC is not implemented, the registers are " \
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"included for compatibility\n", __func__);
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return s->adc_jdr[(addr - ADC_JDR1) / 4] -
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s->adc_jofr[(addr - ADC_JDR1) / 4];
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case ADC_DR:
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if ((s->adc_cr2 & ADC_CR2_ADON) && (s->adc_cr2 & ADC_CR2_SWSTART)) {
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s->adc_cr2 ^= ADC_CR2_SWSTART;
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return stm32f2xx_adc_generate_value(s);
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} else {
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return 0;
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}
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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}
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return 0;
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}
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static void stm32f2xx_adc_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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STM32F2XXADCState *s = opaque;
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uint32_t value = (uint32_t) val64;
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DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n",
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addr, value);
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if (addr >= 0x100) {
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qemu_log_mask(LOG_UNIMP,
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"%s: ADC Common Register Unsupported\n", __func__);
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}
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switch (addr) {
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case ADC_SR:
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s->adc_sr &= (value & 0x3F);
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break;
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case ADC_CR1:
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s->adc_cr1 = value;
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break;
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case ADC_CR2:
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s->adc_cr2 = value;
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break;
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case ADC_SMPR1:
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s->adc_smpr1 = value;
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break;
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case ADC_SMPR2:
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s->adc_smpr2 = value;
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break;
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case ADC_JOFR1:
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case ADC_JOFR2:
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case ADC_JOFR3:
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case ADC_JOFR4:
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s->adc_jofr[(addr - ADC_JOFR1) / 4] = (value & 0xFFF);
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qemu_log_mask(LOG_UNIMP, "%s: " \
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"Injection ADC is not implemented, the registers are " \
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"included for compatibility\n", __func__);
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break;
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case ADC_HTR:
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s->adc_htr = value;
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break;
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case ADC_LTR:
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s->adc_ltr = value;
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break;
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case ADC_SQR1:
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s->adc_sqr1 = value;
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break;
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case ADC_SQR2:
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s->adc_sqr2 = value;
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break;
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case ADC_SQR3:
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s->adc_sqr3 = value;
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break;
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case ADC_JSQR:
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s->adc_jsqr = value;
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qemu_log_mask(LOG_UNIMP, "%s: " \
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"Injection ADC is not implemented, the registers are " \
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"included for compatibility\n", __func__);
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break;
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case ADC_JDR1:
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case ADC_JDR2:
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case ADC_JDR3:
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case ADC_JDR4:
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s->adc_jdr[(addr - ADC_JDR1) / 4] = value;
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qemu_log_mask(LOG_UNIMP, "%s: " \
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"Injection ADC is not implemented, the registers are " \
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"included for compatibility\n", __func__);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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}
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}
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static const MemoryRegionOps stm32f2xx_adc_ops = {
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.read = stm32f2xx_adc_read,
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.write = stm32f2xx_adc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_stm32f2xx_adc = {
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.name = TYPE_STM32F2XX_ADC,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(adc_sr, STM32F2XXADCState),
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VMSTATE_UINT32(adc_cr1, STM32F2XXADCState),
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VMSTATE_UINT32(adc_cr2, STM32F2XXADCState),
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VMSTATE_UINT32(adc_smpr1, STM32F2XXADCState),
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VMSTATE_UINT32(adc_smpr2, STM32F2XXADCState),
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VMSTATE_UINT32_ARRAY(adc_jofr, STM32F2XXADCState, 4),
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VMSTATE_UINT32(adc_htr, STM32F2XXADCState),
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VMSTATE_UINT32(adc_ltr, STM32F2XXADCState),
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VMSTATE_UINT32(adc_sqr1, STM32F2XXADCState),
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VMSTATE_UINT32(adc_sqr2, STM32F2XXADCState),
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VMSTATE_UINT32(adc_sqr3, STM32F2XXADCState),
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VMSTATE_UINT32(adc_jsqr, STM32F2XXADCState),
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VMSTATE_UINT32_ARRAY(adc_jdr, STM32F2XXADCState, 4),
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VMSTATE_UINT32(adc_dr, STM32F2XXADCState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void stm32f2xx_adc_init(Object *obj)
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{
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STM32F2XXADCState *s = STM32F2XX_ADC(obj);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
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memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
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TYPE_STM32F2XX_ADC, 0xFF);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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}
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static void stm32f2xx_adc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = stm32f2xx_adc_reset;
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dc->vmsd = &vmstate_stm32f2xx_adc;
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}
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static const TypeInfo stm32f2xx_adc_info = {
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.name = TYPE_STM32F2XX_ADC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(STM32F2XXADCState),
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.instance_init = stm32f2xx_adc_init,
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.class_init = stm32f2xx_adc_class_init,
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};
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static void stm32f2xx_adc_register_types(void)
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{
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type_register_static(&stm32f2xx_adc_info);
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}
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type_init(stm32f2xx_adc_register_types)
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