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18ff949474
This patch adds handling code for the following SIGP orders: - SIGP SET ARCHITECTURE - SIGP SET PREFIX - SIGP STOP - SIGP STOP AND STORE STATUS - SIGP STORE STATUS AT ADDRESS SIGP STOP (AND STORE STATUS) are the only orders that can stay pending forever (and may only be interrupted by resets), so special care has to be taken about them. Their status also has to be tracked within QEMU. This patch takes care of migrating this status (e.g. if migration happens during a SIGP STOP). Due to the BQL, only one VCPU is currently able to execute SIGP handlers at a time. According to the PoP, BUSY should be returned if another SIGP order is currently being executed on a VCPU. This can only be implemented when the BQL does not protect all handlers. For now, all SIGP orders on all VCPUs will be serialized, which will be okay for the first shot. Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <1424783731-43426-7-git-send-email-jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
349 lines
9.0 KiB
C
349 lines
9.0 KiB
C
/*
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* QEMU S/390 CPU
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*
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* Copyright (c) 2009 Ulrich Hecht
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* Copyright (c) 2011 Alexander Graf
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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* Copyright (c) 2012 IBM Corp.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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* Contributions after 2012-12-11 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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#include "qemu/timer.h"
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#include "qemu/error-report.h"
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#include "hw/hw.h"
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#include "trace.h"
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#ifndef CONFIG_USER_ONLY
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#include "sysemu/arch_init.h"
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#endif
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#define CR0_RESET 0xE0UL
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#define CR14_RESET 0xC2000000UL;
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/* generate CPU information for cpu -? */
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void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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#ifdef CONFIG_KVM
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(*cpu_fprintf)(f, "s390 %16s\n", "host");
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
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{
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CpuDefinitionInfoList *entry;
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CpuDefinitionInfo *info;
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info = g_malloc0(sizeof(*info));
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info->name = g_strdup("host");
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entry = g_malloc0(sizeof(*entry));
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entry->value = info;
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return entry;
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}
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#endif
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static void s390_cpu_set_pc(CPUState *cs, vaddr value)
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{
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S390CPU *cpu = S390_CPU(cs);
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cpu->env.psw.addr = value;
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}
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static bool s390_cpu_has_work(CPUState *cs)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->psw.mask & PSW_MASK_EXT);
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}
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#if !defined(CONFIG_USER_ONLY)
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/* S390CPUClass::load_normal() */
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static void s390_cpu_load_normal(CPUState *s)
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{
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S390CPU *cpu = S390_CPU(s);
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cpu->env.psw.addr = ldl_phys(s->as, 4) & PSW_MASK_ESA_ADDR;
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cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64;
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s390_cpu_set_state(CPU_STATE_OPERATING, cpu);
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}
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#endif
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/* S390CPUClass::cpu_reset() */
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static void s390_cpu_reset(CPUState *s)
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{
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S390CPU *cpu = S390_CPU(s);
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S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
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CPUS390XState *env = &cpu->env;
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env->pfault_token = -1UL;
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scc->parent_reset(s);
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cpu->env.sigp_order = 0;
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s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
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tlb_flush(s, 1);
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}
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/* S390CPUClass::initial_reset() */
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static void s390_cpu_initial_reset(CPUState *s)
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{
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S390CPU *cpu = S390_CPU(s);
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CPUS390XState *env = &cpu->env;
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s390_cpu_reset(s);
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/* initial reset does not touch regs,fregs and aregs */
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memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) -
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offsetof(CPUS390XState, fpc));
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/* architectured initial values for CR 0 and 14 */
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env->cregs[0] = CR0_RESET;
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env->cregs[14] = CR14_RESET;
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env->pfault_token = -1UL;
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/* Reset state inside the kernel that we cannot access yet from QEMU. */
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if (kvm_enabled()) {
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kvm_s390_reset_vcpu(cpu);
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}
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}
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/* CPUClass:reset() */
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static void s390_cpu_full_reset(CPUState *s)
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{
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S390CPU *cpu = S390_CPU(s);
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S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
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CPUS390XState *env = &cpu->env;
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scc->parent_reset(s);
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cpu->env.sigp_order = 0;
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s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
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memset(env, 0, offsetof(CPUS390XState, cpu_num));
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/* architectured initial values for CR 0 and 14 */
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env->cregs[0] = CR0_RESET;
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env->cregs[14] = CR14_RESET;
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env->pfault_token = -1UL;
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/* Reset state inside the kernel that we cannot access yet from QEMU. */
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if (kvm_enabled()) {
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kvm_s390_reset_vcpu(cpu);
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}
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tlb_flush(s, 1);
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}
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#if !defined(CONFIG_USER_ONLY)
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static void s390_cpu_machine_reset_cb(void *opaque)
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{
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S390CPU *cpu = opaque;
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run_on_cpu(CPU(cpu), s390_do_cpu_full_reset, CPU(cpu));
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}
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#endif
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static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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S390CPUClass *scc = S390_CPU_GET_CLASS(dev);
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s390_cpu_gdb_init(cs);
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qemu_init_vcpu(cs);
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#if !defined(CONFIG_USER_ONLY)
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run_on_cpu(cs, s390_do_cpu_full_reset, cs);
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#else
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cpu_reset(cs);
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#endif
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scc->parent_realize(dev, errp);
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}
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static void s390_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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S390CPU *cpu = S390_CPU(obj);
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CPUS390XState *env = &cpu->env;
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static bool inited;
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static int cpu_num = 0;
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#if !defined(CONFIG_USER_ONLY)
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struct tm tm;
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#endif
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cs->env_ptr = env;
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cpu_exec_init(env);
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#if !defined(CONFIG_USER_ONLY)
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qemu_register_reset(s390_cpu_machine_reset_cb, cpu);
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qemu_get_timedate(&tm, 0);
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env->tod_offset = TOD_UNIX_EPOCH +
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(time2tod(mktimegm(&tm)) * 1000000000ULL);
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env->tod_basetime = 0;
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env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu);
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env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu);
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s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
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#endif
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env->cpu_num = cpu_num++;
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env->ext_index = -1;
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if (tcg_enabled() && !inited) {
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inited = true;
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s390x_translate_init();
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}
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}
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static void s390_cpu_finalize(Object *obj)
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{
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#if !defined(CONFIG_USER_ONLY)
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S390CPU *cpu = S390_CPU(obj);
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qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu);
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#endif
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}
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#if !defined(CONFIG_USER_ONLY)
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static bool disabled_wait(CPUState *cpu)
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{
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return cpu->halted && !(S390_CPU(cpu)->env.psw.mask &
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(PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK));
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}
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static unsigned s390_count_running_cpus(void)
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{
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CPUState *cpu;
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int nr_running = 0;
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CPU_FOREACH(cpu) {
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uint8_t state = S390_CPU(cpu)->env.cpu_state;
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if (state == CPU_STATE_OPERATING ||
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state == CPU_STATE_LOAD) {
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if (!disabled_wait(cpu)) {
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nr_running++;
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}
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}
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}
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return nr_running;
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}
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unsigned int s390_cpu_halt(S390CPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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trace_cpu_halt(cs->cpu_index);
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if (!cs->halted) {
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cs->halted = 1;
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cs->exception_index = EXCP_HLT;
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}
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return s390_count_running_cpus();
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}
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void s390_cpu_unhalt(S390CPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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trace_cpu_unhalt(cs->cpu_index);
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if (cs->halted) {
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cs->halted = 0;
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cs->exception_index = -1;
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}
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}
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unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
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{
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trace_cpu_set_state(CPU(cpu)->cpu_index, cpu_state);
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switch (cpu_state) {
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case CPU_STATE_STOPPED:
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case CPU_STATE_CHECK_STOP:
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/* halt the cpu for common infrastructure */
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s390_cpu_halt(cpu);
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break;
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case CPU_STATE_OPERATING:
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case CPU_STATE_LOAD:
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/* unhalt the cpu for common infrastructure */
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s390_cpu_unhalt(cpu);
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break;
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default:
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error_report("Requested CPU state is not a valid S390 CPU state: %u",
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cpu_state);
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exit(1);
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}
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if (kvm_enabled() && cpu->env.cpu_state != cpu_state) {
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kvm_s390_set_cpu_state(cpu, cpu_state);
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}
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cpu->env.cpu_state = cpu_state;
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return s390_count_running_cpus();
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}
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#endif
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static void s390_cpu_class_init(ObjectClass *oc, void *data)
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{
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S390CPUClass *scc = S390_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(scc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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scc->parent_realize = dc->realize;
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dc->realize = s390_cpu_realizefn;
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scc->parent_reset = cc->reset;
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#if !defined(CONFIG_USER_ONLY)
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scc->load_normal = s390_cpu_load_normal;
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#endif
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scc->cpu_reset = s390_cpu_reset;
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scc->initial_cpu_reset = s390_cpu_initial_reset;
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cc->reset = s390_cpu_full_reset;
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cc->has_work = s390_cpu_has_work;
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cc->do_interrupt = s390_cpu_do_interrupt;
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cc->dump_state = s390_cpu_dump_state;
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cc->set_pc = s390_cpu_set_pc;
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cc->gdb_read_register = s390_cpu_gdb_read_register;
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cc->gdb_write_register = s390_cpu_gdb_write_register;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = s390_cpu_handle_mmu_fault;
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#else
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cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
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cc->vmsd = &vmstate_s390_cpu;
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cc->write_elf64_note = s390_cpu_write_elf64_note;
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cc->write_elf64_qemunote = s390_cpu_write_elf64_qemunote;
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cc->cpu_exec_interrupt = s390_cpu_exec_interrupt;
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#endif
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cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
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cc->gdb_core_xml_file = "s390x-core64.xml";
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}
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static const TypeInfo s390_cpu_type_info = {
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.name = TYPE_S390_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(S390CPU),
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.instance_init = s390_cpu_initfn,
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.instance_finalize = s390_cpu_finalize,
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.abstract = false,
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.class_size = sizeof(S390CPUClass),
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.class_init = s390_cpu_class_init,
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};
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static void s390_cpu_register_types(void)
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{
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type_register_static(&s390_cpu_type_info);
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}
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type_init(s390_cpu_register_types)
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