xemu/target
Amir Charif 5de56742a3 target/arm: Check access permission to ADDVL/ADDPL/RDVL
These instructions do not trap when SVE is disabled in EL0,
causing them to be executed with wrong size information.

Signed-off-by: Amir Charif <amir.charif@cea.fr>
Message-id: 1552579248-31025-1-git-send-email-amir.charif@cea.fr
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: added 'target/arm' prefix to subject]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-15 11:12:29 +00:00
..
alpha avoid TABs in files that only contain a few 2019-01-11 15:46:56 +01:00
arm target/arm: Check access permission to ADDVL/ADDPL/RDVL 2019-03-15 11:12:29 +00:00
cris avoid TABs in files that only contain a few 2019-01-11 15:46:56 +01:00
hppa target/hppa: exit TB if either Data or Instruction TLB changes 2019-03-12 09:13:43 -07:00
i386 i386: extended the cpuid_level when Intel PT is enabled 2019-03-11 16:33:49 +01:00
lm32 tcg-next queue 2018-06-04 11:28:31 +01:00
m68k target/m68k: Fix LGPL information in the file headers 2019-01-30 14:20:13 +01:00
microblaze target/microblaze: Add props enabling exceptions on failed bus accesses 2019-01-22 03:17:34 -08:00
mips target/mips: Preparing for adding MMI instructions 2019-02-27 14:26:14 +01:00
moxie target/moxie: Fix LGPL information in the file headers 2019-02-06 15:46:11 +01:00
nios2 tcg-next queue 2018-06-04 11:28:31 +01:00
openrisc target/openrisc: Fix LGPL version number 2019-01-30 11:01:36 +01:00
ppc spapr: Use CamelCase properly 2019-03-12 14:33:05 +11:00
riscv target/riscv: Remove decode_RV32_64G() 2019-03-13 10:40:50 +01:00
s390x s390x/tcg: Implement VECTOR UNPACK * 2019-03-11 09:31:01 +01:00
sh4 sh4: fix use_icount with linux-user 2018-08-20 00:11:06 +02:00
sparc qdev-props: remove errp from GlobalProperty 2019-01-07 16:18:42 +04:00
tilegx avoid TABs in files that only contain a few 2019-01-11 15:46:56 +01:00
tricore tricore: fixed RCR_CADDN instruction 2019-03-08 10:00:59 +01:00
unicore32 target/unicore32: remove tlb_flush from uc32_init_fn 2018-10-18 18:58:10 -07:00
xtensa target/xtensa: implement PREFCTL SR 2019-02-28 04:43:22 -08:00