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xemu/target/riscv/insn_trans
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Weiwei Li f32d82f6c3 target/riscv: optimize helper for vmv<nr>r.v 
LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmv<nr>r.v can share
the same helper

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220325085902.29500-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-22 10:35:16 +10:00
..
trans_privileged.c.inc
target/riscv: Sign extend pc for different XLEN
2022-01-21 15:52:57 +10:00
trans_rva.c.inc
target/riscv: Calculate address according to XLEN
2022-01-21 15:52:57 +10:00
trans_rvb.c.inc
target/riscv: fix inverted checks for ext_zb[abcs]
2022-03-03 13:14:50 +10:00
trans_rvd.c.inc
target/riscv: add support for zdinx
2022-03-03 13:14:50 +10:00
trans_rvf.c.inc
target/riscv: add support for zfinx
2022-03-03 13:14:50 +10:00
trans_rvh.c.inc
exec/memop: Adding signedness to quad definitions
2022-01-08 15:46:10 +10:00
trans_rvi.c.inc
target/riscv: access configuration through cfg_ptr in DisasContext
2022-02-16 12:24:18 +10:00
trans_rvm.c.inc
target/riscv: support for 128-bit M extension
2022-01-08 15:46:10 +10:00
trans_rvv.c.inc
target/riscv: optimize helper for vmv<nr>r.v
2022-04-22 10:35:16 +10:00
trans_rvzfh.c.inc
target/riscv: add support for zhinx/zhinxmin
2022-03-03 13:14:50 +10:00
trans_svinval.c.inc
target/riscv: add support for svinval extension
2022-02-16 12:25:52 +10:00
trans_xventanacondops.c.inc
target/riscv: Add XVentanaCondOps custom extension
2022-02-16 12:24:18 +10:00