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2585c67983
The allwinner code is only needed for the allwinner board (for which we also have a separate CONFIG_ALLWINNER_A10 config switch), so it does not make sense that we compile this for all the other boards that need AHCI, too. Let's move it to a separate file that is only compiled when CONFIG_ALLWINNER_A10 is set. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1508784509-29377-1-git-send-email-thuth@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
128 lines
4.5 KiB
C
128 lines
4.5 KiB
C
/*
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* QEMU Allwinner AHCI Emulation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "qemu/error-report.h"
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#include "sysemu/block-backend.h"
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#include "sysemu/dma.h"
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#include "hw/ide/internal.h"
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#include "hw/ide/ahci_internal.h"
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#include "trace.h"
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#define ALLWINNER_AHCI_BISTAFR ((0xa0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_BISTCR ((0xa4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_BISTFCTR ((0xa8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_BISTSR ((0xac - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_BISTDECR ((0xb0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_DIAGNR0 ((0xb4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_DIAGNR1 ((0xb8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_OOBR ((0xbc - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_PHYCS0R ((0xc0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_PHYCS1R ((0xc4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_PHYCS2R ((0xc8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_TIMER1MS ((0xe0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_GPARAM1R ((0xe8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_GPARAM2R ((0xec - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_PPARAMR ((0xf0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_TESTR ((0xf4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_VERSIONR ((0xf8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_IDR ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_RWCR ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)
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static uint64_t allwinner_ahci_mem_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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AllwinnerAHCIState *a = opaque;
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AHCIState *s = &(SYSBUS_AHCI(a)->ahci);
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uint64_t val = a->regs[addr / 4];
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switch (addr / 4) {
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case ALLWINNER_AHCI_PHYCS0R:
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val |= 0x2 << 28;
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break;
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case ALLWINNER_AHCI_PHYCS2R:
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val &= ~(0x1 << 24);
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break;
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}
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trace_allwinner_ahci_mem_read(s, a, addr, val, size);
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return val;
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}
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static void allwinner_ahci_mem_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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AllwinnerAHCIState *a = opaque;
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AHCIState *s = &(SYSBUS_AHCI(a)->ahci);
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trace_allwinner_ahci_mem_write(s, a, addr, val, size);
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a->regs[addr / 4] = val;
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}
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static const MemoryRegionOps allwinner_ahci_mem_ops = {
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.read = allwinner_ahci_mem_read,
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.write = allwinner_ahci_mem_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void allwinner_ahci_init(Object *obj)
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{
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SysbusAHCIState *s = SYSBUS_AHCI(obj);
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AllwinnerAHCIState *a = ALLWINNER_AHCI(obj);
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memory_region_init_io(&a->mmio, OBJECT(obj), &allwinner_ahci_mem_ops, a,
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"allwinner-ahci", ALLWINNER_AHCI_MMIO_SIZE);
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memory_region_add_subregion(&s->ahci.mem, ALLWINNER_AHCI_MMIO_OFF,
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&a->mmio);
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}
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static const VMStateDescription vmstate_allwinner_ahci = {
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.name = "allwinner-ahci",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AllwinnerAHCIState,
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ALLWINNER_AHCI_MMIO_SIZE / 4),
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VMSTATE_END_OF_LIST()
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}
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};
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static void allwinner_ahci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_allwinner_ahci;
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}
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static const TypeInfo allwinner_ahci_info = {
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.name = TYPE_ALLWINNER_AHCI,
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.parent = TYPE_SYSBUS_AHCI,
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.instance_size = sizeof(AllwinnerAHCIState),
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.instance_init = allwinner_ahci_init,
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.class_init = allwinner_ahci_class_init,
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};
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static void sysbus_ahci_register_types(void)
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{
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type_register_static(&allwinner_ahci_info);
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}
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type_init(sysbus_ahci_register_types)
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