Daniel P. Berrangé d4715481de i386: clarify that the Q35 machine type implements a P35 chipset ... The 'q35' machine type implements an Intel Series 3 chipset, of which there are several variants: https://www.intel.com/Assets/PDF/datasheet/316966.pdf The key difference between the 82P35 MCH ('p35', PCI device ID 0x29c0) and 82Q35 GMCH ('q35', PCI device ID 0x29b0) variants is that the latter has an integrated graphics adapter. QEMU does not implement integrated graphics, so uses the PCI ID for the 82P35 chipset, despite calling the machine type 'q35'. Thus we rename the PCI device ID constant to reflect reality, to avoid confusing future developers. The new name more closely matches what pci.ids reports it to be: $ grep P35 /usr/share/hwdata/pci.ids | grep 29 29c0 82G33/G31/P35/P31 Express DRAM Controller 29c1 82G33/G31/P35/P31 Express PCI Express Root Port 29c4 82G33/G31/P35/P31 Express MEI Controller 29c5 82G33/G31/P35/P31 Express MEI Controller 29c6 82G33/G31/P35/P31 Express PT IDER Controller 29c7 82G33/G31/P35/P31 Express Serial KT Controller $ grep Q35 /usr/share/hwdata/pci.ids | grep 29 29b0 82Q35 Express DRAM Controller 29b1 82Q35 Express PCI Express Root Port 29b2 82Q35 Express Integrated Graphics Controller 29b3 82Q35 Express Integrated Graphics Controller 29b4 82Q35 Express MEI Controller 29b5 82Q35 Express MEI Controller 29b6 82Q35 Express PT IDER Controller 29b7 82Q35 Express Serial KT Controller Arguably the QEMU machine type should be named 'p35'. At this point in time, however, it is not worth the churn for management applications & documentation to worry about renaming it. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20180830105757.10577-1-berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2018-11-06 21:35:05 +01:00
..
bonito.c	hw/pci-host/bonito: Use DeviceState::realize rather than SysBusDevice::init	2018-10-24 06:44:59 -03:00
designware.c	pci: Add support for Designware IP block	2018-03-09 17:09:43 +00:00
gpex.c	pci: Rename root bus initialization functions for clarity	2017-12-05 19:13:45 +02:00
grackle.c	grackle: set device fw_name and address for correct fw path generation	2018-08-30 10:42:18 +10:00
Makefile.objs	pci: Add support for Designware IP block	2018-03-09 17:09:43 +00:00
pam.c	x86: Clean up includes	2016-01-29 15:07:22 +00:00
piix.c	hw/pci-host: Remove useless parenthesis around DIV_ROUND_UP macro	2018-10-26 17:17:32 +02:00
ppce500.c	Merge remote-tracking branch 'origin/master' into HEAD	2018-01-11 22:03:50 +02:00
prep.c	40p: use OR gate to wire up raven PCI interrupts	2018-09-25 11:12:25 +10:00
q35.c	i386: clarify that the Q35 machine type implements a P35 chipset	2018-11-06 21:35:05 +01:00
sabre.c	sabre: generate correct fw path for sabre PCI host bridge	2018-09-14 09:18:05 +01:00
trace-events	uninorth: create new uninorth device	2018-05-04 15:00:37 +10:00
uninorth.c	uninorth: add ofw-addr property to allow correct fw path generation	2018-08-30 10:42:18 +10:00
versatile.c	hw: Do not include "exec/address-spaces.h" if it is not necessary	2018-06-01 14:15:10 +02:00
xilinx-pcie.c	hw/mips: Use the IEC binary prefix definitions	2018-07-02 15:41:16 +02:00