xemu/target-mips
Leon Alrae d54a299b83 target-mips: correct MTC0 instruction on MIPS64
MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0
register.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-09-18 09:20:48 +01:00
..
2015-09-11 10:45:43 +03:00
2012-10-31 21:37:24 +01:00