Emilio G. Cota da94123fe1 target/sh4: fetch code with translator_ld ... There is a small wrinkle with the gUSA instruction. The translator effectively treats a (known) gUSA sequence as a single instruction. For the purposes of the plugin we end up with a long multi-instruction qemu_plugin_insn. If the known sequence isn't detected we shall never run this translation anyway. Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>		2019-10-28 15:12:38 +00:00
..
alpha	target/alpha: Tidy helper_fp_exc_raise_s	2019-09-26 19:00:53 +01:00
arm	target/arm: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
cris	cputlb: ensure _cmmu helper functions follow the naming standard	2019-10-28 15:12:38 +00:00
hppa	target/hppa: prevent trashing of temporary in do_depw_sar()	2019-09-14 15:39:24 -04:00
i386	i386: implement IGNNE	2019-10-26 15:38:07 +02:00
lm32
m68k	target/m68k/fpu_helper.c: rename the access arguments	2019-09-19 12:12:19 +02:00
microblaze	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
mips	target/mips: Refactor handling of vector compare 'less than' (signed) instructions	2019-10-25 18:37:01 +02:00
moxie
nios2
openrisc	target/openrisc: Update cpu "any" to v1.3	2019-09-04 13:01:56 -07:00
ppc	target/ppc: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
riscv	gdbstub: riscv: fix the fflags registers	2019-09-17 08:42:50 -07:00
s390x	s390x/kvm: Set default cpu model for all machine classes	2019-10-21 18:03:08 +02:00
sh4	target/sh4: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
sparc	target/sparc: Switch to do_transaction_failed() hook	2019-09-17 12:01:00 +01:00
tilegx	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
tricore	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
unicore32
xtensa	target/xtensa: regenerate and re-import test_mmuhifi_c3 core	2019-10-18 19:54:27 -07:00