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71c3c44bc3
Switch the ppc405_uc boards to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. We retain the API feature of ppc405ep_init() where it passes back something allowing the callers to wire up devices to the UIC if they need to, even though neither of the callsites currently makes use of this ability -- instead of passing back the qemu_irq array we pass back the UIC DeviceState. This fixes a trivial Coverity-detected memory leak where we were leaking the array of IRQs returned by ppcuic_init(). Fixes: Coverity CID 1421922 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210108171212.16500-4-peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
73 lines
2.5 KiB
C
73 lines
2.5 KiB
C
/*
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* QEMU PowerPC 405 shared definitions
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef PPC405_H
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#define PPC405_H
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#include "hw/ppc/ppc4xx.h"
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/* Bootinfo as set-up by u-boot */
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typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
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struct ppc4xx_bd_info_t {
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uint32_t bi_memstart;
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uint32_t bi_memsize;
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uint32_t bi_flashstart;
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uint32_t bi_flashsize;
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uint32_t bi_flashoffset; /* 0x10 */
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uint32_t bi_sramstart;
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uint32_t bi_sramsize;
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uint32_t bi_bootflags;
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uint32_t bi_ipaddr; /* 0x20 */
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uint8_t bi_enetaddr[6];
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uint16_t bi_ethspeed;
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uint32_t bi_intfreq;
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uint32_t bi_busfreq; /* 0x30 */
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uint32_t bi_baudrate;
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uint8_t bi_s_version[4];
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uint8_t bi_r_version[32];
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uint32_t bi_procfreq;
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uint32_t bi_plb_busfreq;
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uint32_t bi_pci_busfreq;
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uint8_t bi_pci_enetaddr[6];
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uint32_t bi_pci_enetaddr2[6];
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uint32_t bi_opbfreq;
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uint32_t bi_iic_fast[2];
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};
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/* PowerPC 405 core */
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ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
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uint32_t flags);
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void ppc4xx_plb_init(CPUPPCState *env);
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void ppc405_ebc_init(CPUPPCState *env);
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CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
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MemoryRegion ram_memories[2],
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hwaddr ram_bases[2],
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hwaddr ram_sizes[2],
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uint32_t sysclk, DeviceState **uicdev,
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int do_init);
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#endif /* PPC405_H */
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