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6af0bf9c7c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1464 c046a42c-6fe2-441c-8c8c-71466251a162
59 lines
1.9 KiB
C
59 lines
1.9 KiB
C
#if !defined (__QEMU_MIPS_DEFS_H__)
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#define __QEMU_MIPS_DEFS_H__
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/* If we want to use 64 bits host regs... */
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//#define USE_64BITS_REGS
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/* If we want to use host float regs... */
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//#define USE_HOST_FLOAT_REGS
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enum {
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MIPS_R4Kc = 0x00018000,
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MIPS_R4Kp = 0x00018300,
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};
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/* Emulate MIPS R4Kc for now */
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#define MIPS_CPU MIPS_R4Kc
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#if (MIPS_CPU == MIPS_R4Kc)
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/* 32 bits target */
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#define TARGET_LONG_BITS 32
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/* real pages are variable size... */
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#define TARGET_PAGE_BITS 12
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/* Uses MIPS R4Kx ehancements to MIPS32 architecture */
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#define MIPS_USES_R4K_EXT
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/* Uses MIPS R4Kc TLB model */
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#define MIPS_USES_R4K_TLB
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#define MIPS_TLB_NB 16
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/* Have config1, runs in big-endian mode, uses TLB */
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#define MIPS_CONFIG0 \
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((1 << CP0C0_M) | (0x000 << CP0C0_K23) | (0x000 << CP0C0_KU) | \
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(1 << CP0C0_BE) | (0x001 << CP0C0_MT) | (0x010 << CP0C0_K0))
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/* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,
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* 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
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* no performance counters, watch registers present, no code compression,
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* EJTAG present, no FPU
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*/
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#define MIPS_CONFIG1 \
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((15 << CP0C1_MMU) | \
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(0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \
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(0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \
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(0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) | \
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(1 << CP0C1_EP) | (0 << CP0C1_FP))
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#elif defined (MIPS_CPU == MIPS_R4Kp)
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/* 32 bits target */
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#define TARGET_LONG_BITS 32
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/* real pages are variable size... */
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#define TARGET_PAGE_BITS 12
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/* Uses MIPS R4Kx ehancements to MIPS32 architecture */
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#define MIPS_USES_R4K_EXT
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/* Uses MIPS R4Km FPM MMU model */
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#define MIPS_USES_R4K_FPM
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#else
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#error "MIPS CPU not defined"
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/* Remainder for other flags */
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//#define TARGET_MIPS64
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//define MIPS_USES_FPU
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#endif
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#endif /* !defined (__QEMU_MIPS_DEFS_H__) */
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