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bc9ed47b12
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1466 c046a42c-6fe2-441c-8c8c-71466251a162
1506 lines
42 KiB
C
1506 lines
42 KiB
C
/*
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* MIPS32 emulation for qemu: main translation routines.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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#define MIPS_DEBUG_DISAS
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//#define MIPS_SINGLE_STEP
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enum {
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#define DEF(s, n, copy_size) INDEX_op_ ## s,
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#include "opc.h"
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#undef DEF
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NB_OPS,
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};
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
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#include "gen-op.h"
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const unsigned char *regnames[] =
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{ "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
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"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
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"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
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/* Warning: no function for r0 register (hard wired to zero) */
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#define GEN32(func, NAME) \
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static GenOpFunc *NAME ## _table [32] = { \
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NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
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NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
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NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
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NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
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}; \
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static inline void func(int n) \
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{ \
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NAME ## _table[n](); \
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}
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/* General purpose registers moves */
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GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
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GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
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GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
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GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
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GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
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typedef struct DisasContext {
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struct TranslationBlock *tb;
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target_ulong pc, saved_pc;
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uint32_t opcode;
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/* Routine used to access memory */
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int mem_idx;
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uint32_t hflags, saved_hflags;
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uint32_t CP0_Status;
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int bstate;
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target_ulong btarget;
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} DisasContext;
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enum {
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BS_NONE = 0, /* We go out of the TB without reaching a branch or an
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* exception condition
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*/
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BS_STOP = 1, /* We want to stop translation for any reason */
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BS_BRANCH = 2, /* We reached a branch condition */
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BS_EXCP = 3, /* We reached an exception condition */
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};
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#if defined MIPS_DEBUG_DISAS
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#define MIPS_DEBUG(fmt, args...) \
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do { \
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if (loglevel & CPU_LOG_TB_IN_ASM) { \
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fprintf(logfile, "%08x: %08x " fmt "\n", \
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ctx->pc, ctx->opcode , ##args); \
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} \
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} while (0)
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#else
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#define MIPS_DEBUG(fmt, args...) do { } while(0)
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#endif
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#define MIPS_INVAL(op) \
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do { \
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MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
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ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
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} while (0)
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#define GEN_LOAD_REG_TN(Tn, Rn) \
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do { \
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if (Rn == 0) { \
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glue(gen_op_reset_, Tn)(); \
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} else { \
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glue(gen_op_load_gpr_, Tn)(Rn); \
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} \
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} while (0)
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#define GEN_LOAD_IMM_TN(Tn, Imm) \
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do { \
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if (Imm == 0) { \
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glue(gen_op_reset_, Tn)(); \
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} else { \
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glue(gen_op_set_, Tn)(Imm); \
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} \
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} while (0)
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#define GEN_STORE_TN_REG(Rn, Tn) \
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do { \
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if (Rn != 0) { \
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glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
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} \
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} while (0)
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static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
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{
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#if defined MIPS_DEBUG_DISAS
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "hflags %08x saved %08x\n",
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ctx->hflags, ctx->saved_hflags);
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}
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#endif
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if (do_save_pc && ctx->pc != ctx->saved_pc) {
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gen_op_save_pc(ctx->pc);
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ctx->saved_pc = ctx->pc;
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}
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if (ctx->hflags != ctx->saved_hflags) {
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gen_op_save_state(ctx->hflags);
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ctx->saved_hflags = ctx->hflags;
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if (ctx->hflags & MIPS_HFLAG_BR) {
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gen_op_save_breg_target();
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} else if (ctx->hflags & MIPS_HFLAG_B) {
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gen_op_save_btarget(ctx->btarget);
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} else if (ctx->hflags & MIPS_HFLAG_BMASK) {
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gen_op_save_bcond();
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gen_op_save_btarget(ctx->btarget);
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}
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}
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}
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static inline void generate_exception (DisasContext *ctx, int excp)
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{
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#if defined MIPS_DEBUG_DISAS
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile, "%s: raise exception %d\n", __func__, excp);
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#endif
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save_cpu_state(ctx, 1);
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gen_op_raise_exception(excp);
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ctx->bstate = BS_EXCP;
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}
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#if defined(CONFIG_USER_ONLY)
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#define op_ldst(name) gen_op_##name##_raw()
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#define OP_LD_TABLE(width)
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#define OP_ST_TABLE(width)
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#else
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#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
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#define OP_LD_TABLE(width) \
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static GenOpFunc *gen_op_l##width[] = { \
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&gen_op_l##width##_user, \
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&gen_op_l##width##_kernel, \
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}
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#define OP_ST_TABLE(width) \
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static GenOpFunc *gen_op_s##width[] = { \
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&gen_op_s##width##_user, \
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&gen_op_s##width##_kernel, \
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}
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#endif
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#ifdef TARGET_MIPS64
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OP_LD_TABLE(d);
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OP_LD_TABLE(dl);
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OP_LD_TABLE(dr);
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OP_ST_TABLE(d);
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OP_ST_TABLE(dl);
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OP_ST_TABLE(dr);
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#endif
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OP_LD_TABLE(w);
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OP_LD_TABLE(wl);
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OP_LD_TABLE(wr);
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OP_ST_TABLE(w);
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OP_ST_TABLE(wl);
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OP_ST_TABLE(wr);
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OP_LD_TABLE(h);
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OP_LD_TABLE(hu);
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OP_ST_TABLE(h);
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OP_LD_TABLE(b);
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OP_LD_TABLE(bu);
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OP_ST_TABLE(b);
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OP_LD_TABLE(l);
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OP_ST_TABLE(c);
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/* Load and store */
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static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt,
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int base, int16_t offset)
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{
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const unsigned char *opn = "unk";
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if (base == 0) {
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GEN_LOAD_IMM_TN(T0, offset);
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} else if (offset == 0) {
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gen_op_load_gpr_T0(base);
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} else {
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gen_op_load_gpr_T0(base);
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gen_op_set_T1(offset);
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gen_op_add();
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}
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/* Don't do NOP if destination is zero: we must perform the actual
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* memory access
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*/
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switch (opc) {
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#if defined(TARGET_MIPS64)
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case OPC_LD:
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#if defined (MIPS_HAS_UNALIGNED_LS)
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case OPC_ULD:
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#endif
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op_ldst(ld);
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GEN_STORE_TN_REG(rt, T0);
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opn = "ld";
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break;
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case OPC_SD:
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#if defined (MIPS_HAS_UNALIGNED_LS)
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case OPC_USD:
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#endif
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GEN_LOAD_REG_TN(T1, rt);
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op_ldst(sd);
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opn = "sd";
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break;
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case OPC_LDL:
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op_ldst(ldl);
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GEN_STORE_TN_REG(rt, T0);
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opn = "ldl";
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break;
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case OPC_SDL:
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GEN_LOAD_REG_TN(T1, rt);
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op_ldst(sdl);
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opn = "sdl";
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break;
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case OPC_LDR:
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op_ldst(ldr);
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GEN_STORE_TN_REG(rt, T0);
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opn = "ldr";
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break;
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case OPC_SDR:
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GEN_LOAD_REG_TN(T1, rt);
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op_ldst(sdr);
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opn = "sdr";
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break;
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#endif
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case OPC_LW:
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#if defined (MIPS_HAS_UNALIGNED_LS)
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case OPC_ULW:
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#endif
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op_ldst(lw);
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GEN_STORE_TN_REG(rt, T0);
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opn = "lw";
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break;
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case OPC_SW:
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#if defined (MIPS_HAS_UNALIGNED_LS)
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case OPC_USW:
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#endif
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GEN_LOAD_REG_TN(T1, rt);
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op_ldst(sw);
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opn = "sw";
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break;
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case OPC_LH:
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#if defined (MIPS_HAS_UNALIGNED_LS)
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case OPC_ULH:
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#endif
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op_ldst(lh);
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GEN_STORE_TN_REG(rt, T0);
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opn = "lh";
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break;
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case OPC_SH:
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#if defined (MIPS_HAS_UNALIGNED_LS)
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case OPC_USH:
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#endif
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GEN_LOAD_REG_TN(T1, rt);
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op_ldst(sh);
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opn = "sh";
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break;
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case OPC_LHU:
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#if defined (MIPS_HAS_UNALIGNED_LS)
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case OPC_ULHU:
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#endif
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op_ldst(lhu);
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GEN_STORE_TN_REG(rt, T0);
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opn = "lhu";
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break;
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case OPC_LB:
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op_ldst(lb);
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GEN_STORE_TN_REG(rt, T0);
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opn = "lb";
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break;
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case OPC_SB:
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GEN_LOAD_REG_TN(T1, rt);
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op_ldst(sb);
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opn = "sb";
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break;
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case OPC_LBU:
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op_ldst(lbu);
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GEN_STORE_TN_REG(rt, T0);
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opn = "lbu";
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break;
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case OPC_LWL:
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op_ldst(lwl);
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GEN_STORE_TN_REG(rt, T0);
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opn = "lwl";
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break;
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case OPC_SWL:
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GEN_LOAD_REG_TN(T1, rt);
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op_ldst(swl);
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opn = "swr";
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break;
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case OPC_LWR:
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op_ldst(lwr);
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GEN_STORE_TN_REG(rt, T0);
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opn = "lwr";
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break;
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case OPC_SWR:
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GEN_LOAD_REG_TN(T1, rt);
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op_ldst(swr);
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opn = "swr";
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break;
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case OPC_LL:
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op_ldst(ll);
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GEN_STORE_TN_REG(rt, T0);
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opn = "ll";
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break;
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case OPC_SC:
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GEN_LOAD_REG_TN(T1, rt);
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op_ldst(sc);
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GEN_STORE_TN_REG(rt, T0);
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opn = "sc";
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break;
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default:
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MIPS_INVAL("load/store");
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generate_exception(ctx, EXCP_RI);
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return;
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}
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MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
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}
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/* Arithmetic with immediate operand */
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static void gen_arith_imm (DisasContext *ctx, uint16_t opc, int rt,
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int rs, int16_t imm)
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{
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uint32_t uimm;
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const unsigned char *opn = "unk";
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if (rt == 0 && opc != OPC_ADDI) {
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/* if no destination, treat it as a NOP
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* For addi, we must generate the overflow exception when needed.
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*/
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MIPS_DEBUG("NOP");
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return;
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}
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if (opc == OPC_ADDI || opc == OPC_ADDIU ||
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opc == OPC_SLTI || opc == OPC_SLTIU)
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uimm = (int32_t)imm; /* Sign extent to 32 bits */
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else
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uimm = (uint16_t)imm;
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if (opc != OPC_LUI) {
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GEN_LOAD_REG_TN(T0, rs);
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GEN_LOAD_IMM_TN(T1, uimm);
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} else {
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uimm = uimm << 16;
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GEN_LOAD_IMM_TN(T0, uimm);
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}
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switch (opc) {
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case OPC_ADDI:
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save_cpu_state(ctx, 1);
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gen_op_addo();
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opn = "addi";
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break;
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case OPC_ADDIU:
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gen_op_add();
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opn = "addiu";
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break;
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case OPC_SLTI:
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gen_op_lt();
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opn = "slti";
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break;
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case OPC_SLTIU:
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gen_op_ltu();
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opn = "sltiu";
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break;
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case OPC_ANDI:
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gen_op_and();
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opn = "andi";
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break;
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case OPC_ORI:
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gen_op_or();
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opn = "ori";
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break;
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case OPC_XORI:
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gen_op_xor();
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opn = "xori";
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break;
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case OPC_LUI:
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opn = "lui";
|
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break;
|
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case OPC_SLL:
|
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gen_op_sll();
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opn = "sll";
|
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break;
|
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case OPC_SRA:
|
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gen_op_sra();
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opn = "sra";
|
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break;
|
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case OPC_SRL:
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gen_op_srl();
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opn = "srl";
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break;
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default:
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MIPS_INVAL("imm arith");
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generate_exception(ctx, EXCP_RI);
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return;
|
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}
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GEN_STORE_TN_REG(rt, T0);
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MIPS_DEBUG("%s %s, %s, %x", opn, regnames[rt], regnames[rs], uimm);
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}
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|
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/* Arithmetic */
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static void gen_arith (DisasContext *ctx, uint16_t opc,
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int rd, int rs, int rt)
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|
{
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|
const unsigned char *opn = "unk";
|
|
|
|
if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB) {
|
|
/* if no destination, treat it as a NOP
|
|
* For add & sub, we must generate the overflow exception when needed.
|
|
*/
|
|
MIPS_DEBUG("NOP");
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|
return;
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}
|
|
GEN_LOAD_REG_TN(T0, rs);
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GEN_LOAD_REG_TN(T1, rt);
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|
switch (opc) {
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case OPC_ADD:
|
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save_cpu_state(ctx, 1);
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gen_op_addo();
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opn = "add";
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break;
|
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case OPC_ADDU:
|
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gen_op_add();
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opn = "addu";
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break;
|
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case OPC_SUB:
|
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save_cpu_state(ctx, 1);
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gen_op_subo();
|
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opn = "sub";
|
|
break;
|
|
case OPC_SUBU:
|
|
gen_op_sub();
|
|
opn = "subu";
|
|
break;
|
|
case OPC_SLT:
|
|
gen_op_lt();
|
|
opn = "slt";
|
|
break;
|
|
case OPC_SLTU:
|
|
gen_op_ltu();
|
|
opn = "sltu";
|
|
break;
|
|
case OPC_AND:
|
|
gen_op_and();
|
|
opn = "and";
|
|
break;
|
|
case OPC_NOR:
|
|
gen_op_nor();
|
|
opn = "nor";
|
|
break;
|
|
case OPC_OR:
|
|
gen_op_or();
|
|
opn = "or";
|
|
break;
|
|
case OPC_XOR:
|
|
gen_op_xor();
|
|
opn = "xor";
|
|
break;
|
|
case OPC_MUL:
|
|
gen_op_mul();
|
|
opn = "mul";
|
|
break;
|
|
case OPC_MOVN:
|
|
gen_op_movn(rd);
|
|
opn = "movn";
|
|
goto print;
|
|
case OPC_MOVZ:
|
|
gen_op_movz(rd);
|
|
opn = "movz";
|
|
goto print;
|
|
case OPC_SLLV:
|
|
gen_op_sllv();
|
|
opn = "sllv";
|
|
break;
|
|
case OPC_SRAV:
|
|
gen_op_srav();
|
|
opn = "srav";
|
|
break;
|
|
case OPC_SRLV:
|
|
gen_op_srlv();
|
|
opn = "srlv";
|
|
break;
|
|
default:
|
|
MIPS_INVAL("arith");
|
|
generate_exception(ctx, EXCP_RI);
|
|
return;
|
|
}
|
|
GEN_STORE_TN_REG(rd, T0);
|
|
print:
|
|
MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
|
|
}
|
|
|
|
/* Arithmetic on HI/LO registers */
|
|
static void gen_HILO (DisasContext *ctx, uint16_t opc, int reg)
|
|
{
|
|
const unsigned char *opn = "unk";
|
|
|
|
if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
|
|
/* Treat as a NOP */
|
|
MIPS_DEBUG("NOP");
|
|
return;
|
|
}
|
|
switch (opc) {
|
|
case OPC_MFHI:
|
|
gen_op_load_HI();
|
|
GEN_STORE_TN_REG(reg, T0);
|
|
opn = "mfhi";
|
|
break;
|
|
case OPC_MFLO:
|
|
gen_op_load_LO();
|
|
GEN_STORE_TN_REG(reg, T0);
|
|
opn = "mflo";
|
|
break;
|
|
case OPC_MTHI:
|
|
GEN_LOAD_REG_TN(T0, reg);
|
|
gen_op_store_HI();
|
|
opn = "mthi";
|
|
break;
|
|
case OPC_MTLO:
|
|
GEN_LOAD_REG_TN(T0, reg);
|
|
gen_op_store_LO();
|
|
opn = "mtlo";
|
|
break;
|
|
default:
|
|
MIPS_INVAL("HILO");
|
|
generate_exception(ctx, EXCP_RI);
|
|
return;
|
|
}
|
|
MIPS_DEBUG("%s %s", opn, regnames[reg]);
|
|
}
|
|
|
|
static void gen_muldiv (DisasContext *ctx, uint16_t opc,
|
|
int rs, int rt)
|
|
{
|
|
const unsigned char *opn = "unk";
|
|
|
|
GEN_LOAD_REG_TN(T0, rs);
|
|
GEN_LOAD_REG_TN(T1, rt);
|
|
switch (opc) {
|
|
case OPC_DIV:
|
|
gen_op_div();
|
|
opn = "div";
|
|
break;
|
|
case OPC_DIVU:
|
|
gen_op_divu();
|
|
opn = "divu";
|
|
break;
|
|
case OPC_MULT:
|
|
gen_op_mult();
|
|
opn = "mult";
|
|
break;
|
|
case OPC_MULTU:
|
|
gen_op_multu();
|
|
opn = "multu";
|
|
break;
|
|
case OPC_MADD:
|
|
gen_op_madd();
|
|
opn = "madd";
|
|
break;
|
|
case OPC_MADDU:
|
|
gen_op_maddu();
|
|
opn = "maddu";
|
|
break;
|
|
case OPC_MSUB:
|
|
gen_op_msub();
|
|
opn = "msub";
|
|
break;
|
|
case OPC_MSUBU:
|
|
gen_op_msubu();
|
|
opn = "msubu";
|
|
break;
|
|
default:
|
|
MIPS_INVAL("mul/div");
|
|
generate_exception(ctx, EXCP_RI);
|
|
return;
|
|
}
|
|
MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
|
|
}
|
|
|
|
static void gen_cl (DisasContext *ctx, uint16_t opc,
|
|
int rd, int rs)
|
|
{
|
|
const unsigned char *opn = "unk";
|
|
if (rd == 0) {
|
|
/* Treat as a NOP */
|
|
MIPS_DEBUG("NOP");
|
|
return;
|
|
}
|
|
GEN_LOAD_REG_TN(T0, rs);
|
|
switch (opc) {
|
|
case OPC_CLO:
|
|
/* CLO */
|
|
gen_op_clo();
|
|
opn = "clo";
|
|
break;
|
|
case OPC_CLZ:
|
|
/* CLZ */
|
|
gen_op_clz();
|
|
opn = "clz";
|
|
break;
|
|
default:
|
|
MIPS_INVAL("CLx");
|
|
generate_exception(ctx, EXCP_RI);
|
|
return;
|
|
}
|
|
gen_op_store_T0_gpr(rd);
|
|
MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
|
|
}
|
|
|
|
/* Traps */
|
|
static void gen_trap (DisasContext *ctx, uint16_t opc,
|
|
int rs, int rt, int16_t imm)
|
|
{
|
|
int cond;
|
|
|
|
cond = 0;
|
|
/* Load needed operands */
|
|
switch (opc) {
|
|
case OPC_TEQ:
|
|
case OPC_TGE:
|
|
case OPC_TGEU:
|
|
case OPC_TLT:
|
|
case OPC_TLTU:
|
|
case OPC_TNE:
|
|
/* Compare two registers */
|
|
if (rs != rt) {
|
|
GEN_LOAD_REG_TN(T0, rs);
|
|
GEN_LOAD_REG_TN(T1, rt);
|
|
cond = 1;
|
|
}
|
|
case OPC_TEQI:
|
|
case OPC_TGEI:
|
|
case OPC_TGEIU:
|
|
case OPC_TLTI:
|
|
case OPC_TLTIU:
|
|
case OPC_TNEI:
|
|
/* Compare register to immediate */
|
|
if (rs != 0 || imm != 0) {
|
|
GEN_LOAD_REG_TN(T0, rs);
|
|
GEN_LOAD_IMM_TN(T1, (int32_t)imm);
|
|
cond = 1;
|
|
}
|
|
break;
|
|
}
|
|
if (cond == 0) {
|
|
switch (opc) {
|
|
case OPC_TEQ: /* rs == rs */
|
|
case OPC_TEQI: /* r0 == 0 */
|
|
case OPC_TGE: /* rs >= rs */
|
|
case OPC_TGEI: /* r0 >= 0 */
|
|
case OPC_TGEU: /* rs >= rs unsigned */
|
|
case OPC_TGEIU: /* r0 >= 0 unsigned */
|
|
/* Always trap */
|
|
gen_op_set_T0(1);
|
|
break;
|
|
case OPC_TLT: /* rs < rs */
|
|
case OPC_TLTI: /* r0 < 0 */
|
|
case OPC_TLTU: /* rs < rs unsigned */
|
|
case OPC_TLTIU: /* r0 < 0 unsigned */
|
|
case OPC_TNE: /* rs != rs */
|
|
case OPC_TNEI: /* r0 != 0 */
|
|
/* Never trap: treat as NOP */
|
|
return;
|
|
default:
|
|
MIPS_INVAL("TRAP");
|
|
generate_exception(ctx, EXCP_RI);
|
|
return;
|
|
}
|
|
} else {
|
|
switch (opc) {
|
|
case OPC_TEQ:
|
|
case OPC_TEQI:
|
|
gen_op_eq();
|
|
break;
|
|
case OPC_TGE:
|
|
case OPC_TGEI:
|
|
gen_op_ge();
|
|
break;
|
|
case OPC_TGEU:
|
|
case OPC_TGEIU:
|
|
gen_op_geu();
|
|
break;
|
|
case OPC_TLT:
|
|
case OPC_TLTI:
|
|
gen_op_lt();
|
|
break;
|
|
case OPC_TLTU:
|
|
case OPC_TLTIU:
|
|
gen_op_ltu();
|
|
break;
|
|
case OPC_TNE:
|
|
case OPC_TNEI:
|
|
gen_op_ne();
|
|
break;
|
|
default:
|
|
MIPS_INVAL("TRAP");
|
|
generate_exception(ctx, EXCP_RI);
|
|
return;
|
|
}
|
|
}
|
|
save_cpu_state(ctx, 1);
|
|
gen_op_trap();
|
|
ctx->bstate = BS_STOP;
|
|
}
|
|
|
|
/* Branches (before delay slot) */
|
|
static void gen_compute_branch (DisasContext *ctx, uint16_t opc,
|
|
int rs, int rt, int32_t offset)
|
|
{
|
|
target_ulong btarget;
|
|
int blink, bcond;
|
|
|
|
btarget = -1;
|
|
blink = 0;
|
|
bcond = 0;
|
|
/* Load needed operands */
|
|
switch (opc) {
|
|
case OPC_BEQ:
|
|
case OPC_BEQL:
|
|
case OPC_BNE:
|
|
case OPC_BNEL:
|
|
/* Compare two registers */
|
|
if (rs != rt) {
|
|
GEN_LOAD_REG_TN(T0, rs);
|
|
GEN_LOAD_REG_TN(T1, rt);
|
|
bcond = 1;
|
|
}
|
|
btarget = ctx->pc + 4 + offset;
|
|
break;
|
|
case OPC_BGEZ:
|
|
case OPC_BGEZAL:
|
|
case OPC_BGEZALL:
|
|
case OPC_BGEZL:
|
|
case OPC_BGTZ:
|
|
case OPC_BGTZL:
|
|
case OPC_BLEZ:
|
|
case OPC_BLEZL:
|
|
case OPC_BLTZ:
|
|
case OPC_BLTZAL:
|
|
case OPC_BLTZALL:
|
|
case OPC_BLTZL:
|
|
/* Compare to zero */
|
|
if (rs != 0) {
|
|
gen_op_load_gpr_T0(rs);
|
|
bcond = 1;
|
|
}
|
|
btarget = ctx->pc + 4 + offset;
|
|
break;
|
|
case OPC_J:
|
|
case OPC_JAL:
|
|
/* Jump to immediate */
|
|
btarget = ((ctx->pc + 4) & 0xF0000000) | offset;
|
|
break;
|
|
case OPC_JR:
|
|
case OPC_JALR:
|
|
/* Jump to register */
|
|
if (offset != 0) {
|
|
/* Only hint = 0 is valid */
|
|
generate_exception(ctx, EXCP_RI);
|
|
return;
|
|
}
|
|
GEN_LOAD_REG_TN(T2, rs);
|
|
break;
|
|
default:
|
|
MIPS_INVAL("branch/jump");
|
|
generate_exception(ctx, EXCP_RI);
|
|
return;
|
|
}
|
|
if (bcond == 0) {
|
|
/* No condition to be computed */
|
|
switch (opc) {
|
|
case OPC_BEQ: /* rx == rx */
|
|
case OPC_BEQL: /* rx == rx likely */
|
|
case OPC_BGEZ: /* 0 >= 0 */
|
|
case OPC_BGEZL: /* 0 >= 0 likely */
|
|
case OPC_BLEZ: /* 0 <= 0 */
|
|
case OPC_BLEZL: /* 0 <= 0 likely */
|
|
/* Always take */
|
|
ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
|
|
MIPS_DEBUG("balways");
|
|
break;
|
|
case OPC_BGEZAL: /* 0 >= 0 */
|
|
case OPC_BGEZALL: /* 0 >= 0 likely */
|
|
/* Always take and link */
|
|
blink = 31;
|
|
ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
|
|
MIPS_DEBUG("balways and link");
|
|
break;
|
|
case OPC_BNE: /* rx != rx */
|
|
case OPC_BGTZ: /* 0 > 0 */
|
|
case OPC_BLTZ: /* 0 < 0 */
|
|
case OPC_BLTZAL: /* 0 < 0 */
|
|
/* Treated as NOP */
|
|
MIPS_DEBUG("bnever (NOP)");
|
|
return;
|
|
case OPC_BNEL: /* rx != rx likely */
|
|
case OPC_BGTZL: /* 0 > 0 likely */
|
|
case OPC_BLTZALL: /* 0 < 0 likely */
|
|
case OPC_BLTZL: /* 0 < 0 likely */
|
|
/* Skip the instruction in the delay slot */
|
|
MIPS_DEBUG("bnever and skip");
|
|
gen_op_branch((long)ctx->tb, ctx->pc + 4);
|
|
return;
|
|
case OPC_J:
|
|
ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
|
|
MIPS_DEBUG("j %08x", btarget);
|
|
break;
|
|
case OPC_JAL:
|
|
blink = 31;
|
|
ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
|
|
MIPS_DEBUG("jal %08x", btarget);
|
|
break;
|
|
case OPC_JR:
|
|
ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR;
|
|
MIPS_DEBUG("jr %s", regnames[rs]);
|
|
break;
|
|
case OPC_JALR:
|
|
blink = rt;
|
|
ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR;
|
|
MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]);
|
|
break;
|
|
default:
|
|
MIPS_INVAL("branch/jump");
|
|
generate_exception(ctx, EXCP_RI);
|
|
return;
|
|
}
|
|
} else {
|
|
switch (opc) {
|
|
case OPC_BEQ:
|
|
gen_op_eq();
|
|
MIPS_DEBUG("beq %s, %s, %08x",
|
|
regnames[rs], regnames[rt], btarget);
|
|
goto not_likely;
|
|
case OPC_BEQL:
|
|
gen_op_eq();
|
|
MIPS_DEBUG("beql %s, %s, %08x",
|
|
regnames[rs], regnames[rt], btarget);
|
|
goto likely;
|
|
case OPC_BNE:
|
|
gen_op_ne();
|
|
MIPS_DEBUG("bne %s, %s, %08x",
|
|
regnames[rs], regnames[rt], btarget);
|
|
goto not_likely;
|
|
case OPC_BNEL:
|
|
gen_op_ne();
|
|
MIPS_DEBUG("bnel %s, %s, %08x",
|
|
regnames[rs], regnames[rt], btarget);
|
|
goto likely;
|
|
case OPC_BGEZ:
|
|
gen_op_gez();
|
|
MIPS_DEBUG("bgez %s, %08x", regnames[rs], btarget);
|
|
goto not_likely;
|
|
case OPC_BGEZL:
|
|
gen_op_gez();
|
|
MIPS_DEBUG("bgezl %s, %08x", regnames[rs], btarget);
|
|
goto likely;
|
|
case OPC_BGEZAL:
|
|
gen_op_gez();
|
|
MIPS_DEBUG("bgezal %s, %08x", regnames[rs], btarget);
|
|
blink = 31;
|
|
goto not_likely;
|
|
case OPC_BGEZALL:
|
|
gen_op_gez();
|
|
blink = 31;
|
|
MIPS_DEBUG("bgezall %s, %08x", regnames[rs], btarget);
|
|
goto likely;
|
|
case OPC_BGTZ:
|
|
gen_op_gtz();
|
|
MIPS_DEBUG("bgtz %s, %08x", regnames[rs], btarget);
|
|
goto not_likely;
|
|
case OPC_BGTZL:
|
|
gen_op_gtz();
|
|
MIPS_DEBUG("bgtzl %s, %08x", regnames[rs], btarget);
|
|
goto likely;
|
|
case OPC_BLEZ:
|
|
gen_op_lez();
|
|
MIPS_DEBUG("blez %s, %08x", regnames[rs], btarget);
|
|
goto not_likely;
|
|
case OPC_BLEZL:
|
|
gen_op_lez();
|
|
MIPS_DEBUG("blezl %s, %08x", regnames[rs], btarget);
|
|
goto likely;
|
|
case OPC_BLTZ:
|
|
gen_op_ltz();
|
|
MIPS_DEBUG("bltz %s, %08x", regnames[rs], btarget);
|
|
goto not_likely;
|
|
case OPC_BLTZL:
|
|
gen_op_ltz();
|
|
MIPS_DEBUG("bltzl %s, %08x", regnames[rs], btarget);
|
|
goto likely;
|
|
case OPC_BLTZAL:
|
|
gen_op_ltz();
|
|
blink = 31;
|
|
MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget);
|
|
not_likely:
|
|
ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BC;
|
|
break;
|
|
case OPC_BLTZALL:
|
|
gen_op_ltz();
|
|
blink = 31;
|
|
MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget);
|
|
likely:
|
|
ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BL;
|
|
break;
|
|
}
|
|
gen_op_set_bcond();
|
|
}
|
|
MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
|
|
blink, ctx->hflags, btarget);
|
|
ctx->btarget = btarget;
|
|
if (blink > 0) {
|
|
gen_op_set_T0(ctx->pc + 8);
|
|
gen_op_store_T0_gpr(blink);
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* CP0 (MMU and control) */
|
|
static void gen_cp0 (DisasContext *ctx, uint16_t opc, int rt, int rd)
|
|
{
|
|
const unsigned char *opn = "unk";
|
|
|
|
if (!(ctx->CP0_Status & (1 << CP0St_CU0))) {
|
|
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
fprintf(logfile, "CP0 is not usable\n");
|
|
}
|
|
gen_op_raise_exception_err(EXCP_CpU, 0);
|
|
return;
|
|
}
|
|
switch (opc) {
|
|
case OPC_MFC0:
|
|
if (rt == 0) {
|
|
/* Treat as NOP */
|
|
return;
|
|
}
|
|
gen_op_mfc0(rd, ctx->opcode & 0x7);
|
|
gen_op_store_T0_gpr(rt);
|
|
opn = "mfc0";
|
|
break;
|
|
case OPC_MTC0:
|
|
/* If we get an exception, we want to restart at next instruction */
|
|
ctx->pc += 4;
|
|
save_cpu_state(ctx, 1);
|
|
ctx->pc -= 4;
|
|
GEN_LOAD_REG_TN(T0, rt);
|
|
gen_op_mtc0(rd, ctx->opcode & 0x7);
|
|
/* Stop translation as we may have switched the execution mode */
|
|
ctx->bstate = BS_STOP;
|
|
opn = "mtc0";
|
|
break;
|
|
#if defined(MIPS_USES_R4K_TLB)
|
|
case OPC_TLBWI:
|
|
gen_op_tlbwi();
|
|
opn = "tlbwi";
|
|
break;
|
|
case OPC_TLBWR:
|
|
gen_op_tlbwr();
|
|
opn = "tlbwr";
|
|
break;
|
|
case OPC_TLBP:
|
|
gen_op_tlbp();
|
|
opn = "tlbp";
|
|
break;
|
|
case OPC_TLBR:
|
|
gen_op_tlbr();
|
|
opn = "tlbr";
|
|
break;
|
|
#endif
|
|
case OPC_ERET:
|
|
opn = "eret";
|
|
save_cpu_state(ctx, 0);
|
|
gen_op_eret();
|
|
ctx->bstate = BS_EXCP;
|
|
break;
|
|
case OPC_DERET:
|
|
opn = "deret";
|
|
if (!(ctx->hflags & MIPS_HFLAG_DM)) {
|
|
generate_exception(ctx, EXCP_RI);
|
|
} else {
|
|
save_cpu_state(ctx, 0);
|
|
gen_op_deret();
|
|
ctx->bstate = BS_EXCP;
|
|
}
|
|
break;
|
|
/* XXX: TODO: WAIT */
|
|
default:
|
|
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
|
|
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
|
|
((ctx->opcode >> 16) & 0x1F));
|
|
}
|
|
generate_exception(ctx, EXCP_RI);
|
|
return;
|
|
}
|
|
MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
|
|
}
|
|
|
|
/* Coprocessor 1 (FPU) */
|
|
|
|
/* ISA extensions */
|
|
/* MIPS16 extension to MIPS32 */
|
|
/* SmartMIPS extension to MIPS32 */
|
|
|
|
#ifdef TARGET_MIPS64
|
|
static void gen_arith64 (DisasContext *ctx, uint16_t opc)
|
|
{
|
|
if (func == 0x02 && rd == 0) {
|
|
/* NOP */
|
|
return;
|
|
}
|
|
if (rs == 0 || rt == 0) {
|
|
gen_op_reset_T0();
|
|
gen_op_save64();
|
|
} else {
|
|
gen_op_load_gpr_T0(rs);
|
|
gen_op_load_gpr_T1(rt);
|
|
gen_op_save64();
|
|
if (func & 0x01)
|
|
gen_op_mul64u();
|
|
else
|
|
gen_op_mul64s();
|
|
}
|
|
if (func & 0x02)
|
|
gen_op_add64();
|
|
else
|
|
gen_op_sub64();
|
|
}
|
|
|
|
/* Coprocessor 3 (FPU) */
|
|
|
|
/* MDMX extension to MIPS64 */
|
|
/* MIPS-3D extension to MIPS64 */
|
|
|
|
#endif
|
|
|
|
static void decode_opc (DisasContext *ctx)
|
|
{
|
|
int32_t offset;
|
|
int rs, rt, rd, sa;
|
|
uint16_t op, op1;
|
|
int16_t imm;
|
|
|
|
if ((ctx->hflags & MIPS_HFLAG_DS) &&
|
|
(ctx->hflags & MIPS_HFLAG_BL)) {
|
|
/* Handle blikely not taken case */
|
|
MIPS_DEBUG("blikely condition (%08x)", ctx->pc + 4);
|
|
gen_op_blikely((long)ctx->tb, ctx->pc + 4,
|
|
ctx->hflags & ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS));
|
|
}
|
|
op = ctx->opcode >> 26;
|
|
rs = ((ctx->opcode >> 21) & 0x1F);
|
|
rt = ((ctx->opcode >> 16) & 0x1F);
|
|
rd = ((ctx->opcode >> 11) & 0x1F);
|
|
sa = ((ctx->opcode >> 6) & 0x1F);
|
|
imm = (int16_t)ctx->opcode;
|
|
switch (op) {
|
|
case 0x00: /* Special opcode */
|
|
op1 = ctx->opcode & 0x3F;
|
|
switch (op1) {
|
|
case 0x00: /* Arithmetic with immediate */
|
|
case 0x02 ... 0x03:
|
|
gen_arith_imm(ctx, op1 | EXT_SPECIAL, rd, rt, sa);
|
|
break;
|
|
case 0x04: /* Arithmetic */
|
|
case 0x06 ... 0x07:
|
|
case 0x0A ... 0x0B:
|
|
case 0x20 ... 0x27:
|
|
case 0x2A ... 0x2B:
|
|
gen_arith(ctx, op1 | EXT_SPECIAL, rd, rs, rt);
|
|
break;
|
|
case 0x18 ... 0x1B: /* MULT / DIV */
|
|
gen_muldiv(ctx, op1 | EXT_SPECIAL, rs, rt);
|
|
break;
|
|
case 0x08 ... 0x09: /* Jumps */
|
|
gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa);
|
|
return;
|
|
case 0x30 ... 0x34: /* Traps */
|
|
case 0x36:
|
|
gen_trap(ctx, op1 | EXT_SPECIAL, rs, rt, -1);
|
|
break;
|
|
case 0x10: /* Move from HI/LO */
|
|
case 0x12:
|
|
gen_HILO(ctx, op1 | EXT_SPECIAL, rd);
|
|
break;
|
|
case 0x11:
|
|
case 0x13: /* Move to HI/LO */
|
|
gen_HILO(ctx, op1 | EXT_SPECIAL, rs);
|
|
break;
|
|
case 0x0C: /* SYSCALL */
|
|
generate_exception(ctx, EXCP_SYSCALL);
|
|
break;
|
|
case 0x0D: /* BREAK */
|
|
generate_exception(ctx, EXCP_BREAK);
|
|
break;
|
|
case 0x0F: /* SYNC */
|
|
/* Treat as a noop */
|
|
break;
|
|
case 0x05: /* Pmon entry point */
|
|
gen_op_pmon((ctx->opcode >> 6) & 0x1F);
|
|
break;
|
|
#if defined (MIPS_HAS_MOVCI)
|
|
case 0x01: /* MOVCI */
|
|
#endif
|
|
#if defined (TARGET_MIPS64)
|
|
case 0x14: /* MIPS64 specific opcodes */
|
|
case 0x16:
|
|
case 0x17:
|
|
case 0x1C ... 0x1F:
|
|
case 0x2C ... 0x2F:
|
|
case 0x37:
|
|
case 0x39 ... 0x3B:
|
|
case 0x3E ... 0x3F:
|
|
#endif
|
|
default: /* Invalid */
|
|
MIPS_INVAL("special");
|
|
generate_exception(ctx, EXCP_RI);
|
|
break;
|
|
}
|
|
break;
|
|
case 0x1C: /* Special2 opcode */
|
|
op1 = ctx->opcode & 0x3F;
|
|
switch (op1) {
|
|
#if defined (MIPS_USES_R4K_EXT)
|
|
/* Those instructions are not part of MIPS32 core */
|
|
case 0x00 ... 0x01: /* Multiply and add/sub */
|
|
case 0x04 ... 0x05:
|
|
gen_muldiv(ctx, op1 | EXT_SPECIAL2, rs, rt);
|
|
break;
|
|
case 0x02: /* MUL */
|
|
gen_arith(ctx, op1 | EXT_SPECIAL2, rd, rs, rt);
|
|
break;
|
|
case 0x20 ... 0x21: /* CLO / CLZ */
|
|
gen_cl(ctx, op1 | EXT_SPECIAL2, rd, rs);
|
|
break;
|
|
#endif
|
|
case 0x3F: /* SDBBP */
|
|
/* XXX: not clear which exception should be raised
|
|
* when in debug mode...
|
|
*/
|
|
if (!(ctx->hflags & MIPS_HFLAG_DM)) {
|
|
generate_exception(ctx, EXCP_DBp);
|
|
} else {
|
|
generate_exception(ctx, EXCP_DBp);
|
|
}
|
|
/* Treat as a noop */
|
|
break;
|
|
default: /* Invalid */
|
|
MIPS_INVAL("special2");
|
|
generate_exception(ctx, EXCP_RI);
|
|
break;
|
|
}
|
|
break;
|
|
case 0x01: /* B REGIMM opcode */
|
|
op1 = ((ctx->opcode >> 16) & 0x1F);
|
|
switch (op1) {
|
|
case 0x00 ... 0x03: /* REGIMM branches */
|
|
case 0x10 ... 0x13:
|
|
gen_compute_branch(ctx, op1 | EXT_REGIMM, rs, -1, imm << 2);
|
|
return;
|
|
case 0x08 ... 0x0C: /* Traps */
|
|
case 0x0E:
|
|
gen_trap(ctx, op1 | EXT_REGIMM, rs, -1, imm);
|
|
break;
|
|
default: /* Invalid */
|
|
MIPS_INVAL("REGIMM");
|
|
generate_exception(ctx, EXCP_RI);
|
|
break;
|
|
}
|
|
break;
|
|
case 0x10: /* CP0 opcode */
|
|
op1 = ((ctx->opcode >> 21) & 0x1F);
|
|
switch (op1) {
|
|
case 0x00:
|
|
case 0x04:
|
|
gen_cp0(ctx, op1 | EXT_CP0, rt, rd);
|
|
break;
|
|
default:
|
|
gen_cp0(ctx, (ctx->opcode & 0x1F) | EXT_CP0, rt, rd);
|
|
break;
|
|
}
|
|
break;
|
|
case 0x08 ... 0x0F: /* Arithmetic with immediate opcode */
|
|
gen_arith_imm(ctx, op, rt, rs, imm);
|
|
break;
|
|
case 0x02 ... 0x03: /* Jump */
|
|
offset = (int32_t)(ctx->opcode & 0x03FFFFFF) << 2;
|
|
gen_compute_branch(ctx, op, rs, rt, offset);
|
|
return;
|
|
case 0x04 ... 0x07: /* Branch */
|
|
case 0x14 ... 0x17:
|
|
gen_compute_branch(ctx, op, rs, rt, imm << 2);
|
|
return;
|
|
case 0x20 ... 0x26: /* Load and stores */
|
|
case 0x28 ... 0x2E:
|
|
case 0x30:
|
|
case 0x38:
|
|
gen_ldst(ctx, op, rt, rs, imm);
|
|
break;
|
|
case 0x2F: /* Cache operation */
|
|
/* Treat as a noop */
|
|
break;
|
|
case 0x33: /* Prefetch */
|
|
/* Treat as a noop */
|
|
break;
|
|
case 0x3F: /* HACK */
|
|
break;
|
|
#if defined(MIPS_USES_FPU)
|
|
case 0x31 ... 0x32: /* Floating point load/store */
|
|
case 0x35 ... 0x36:
|
|
case 0x3A ... 0x3B:
|
|
case 0x3D ... 0x3E:
|
|
/* Not implemented */
|
|
/* XXX: not correct */
|
|
#endif
|
|
case 0x11: /* CP1 opcode */
|
|
/* Not implemented */
|
|
/* XXX: not correct */
|
|
case 0x12: /* CP2 opcode */
|
|
/* Not implemented */
|
|
/* XXX: not correct */
|
|
case 0x13: /* CP3 opcode */
|
|
/* Not implemented */
|
|
/* XXX: not correct */
|
|
#if defined (TARGET_MIPS64)
|
|
case 0x18 ... 0x1B:
|
|
case 0x27:
|
|
case 0x34:
|
|
case 0x37:
|
|
/* MIPS64 opcodes */
|
|
#endif
|
|
#if defined (MIPS_HAS_JALX)
|
|
case 0x1D:
|
|
/* JALX: not implemented */
|
|
#endif
|
|
case 0x1E:
|
|
/* ASE specific */
|
|
#if defined (MIPS_HAS_LSC)
|
|
case 0x31: /* LWC1 */
|
|
case 0x32: /* LWC2 */
|
|
case 0x35: /* SDC1 */
|
|
case 0x36: /* SDC2 */
|
|
#endif
|
|
default: /* Invalid */
|
|
MIPS_INVAL("");
|
|
generate_exception(ctx, EXCP_RI);
|
|
break;
|
|
}
|
|
if (ctx->hflags & MIPS_HFLAG_DS) {
|
|
int hflags = ctx->hflags;
|
|
/* Branches completion */
|
|
ctx->hflags &= ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS);
|
|
ctx->bstate = BS_BRANCH;
|
|
save_cpu_state(ctx, 0);
|
|
switch (hflags & MIPS_HFLAG_BMASK) {
|
|
case MIPS_HFLAG_B:
|
|
/* unconditional branch */
|
|
MIPS_DEBUG("unconditional branch");
|
|
gen_op_branch((long)ctx->tb, ctx->btarget);
|
|
break;
|
|
case MIPS_HFLAG_BL:
|
|
/* blikely taken case */
|
|
MIPS_DEBUG("blikely branch taken");
|
|
gen_op_branch((long)ctx->tb, ctx->btarget);
|
|
break;
|
|
case MIPS_HFLAG_BC:
|
|
/* Conditional branch */
|
|
MIPS_DEBUG("conditional branch");
|
|
gen_op_bcond((long)ctx->tb, ctx->btarget, ctx->pc + 4);
|
|
break;
|
|
case MIPS_HFLAG_BR:
|
|
/* unconditional branch to register */
|
|
MIPS_DEBUG("branch to register");
|
|
gen_op_breg();
|
|
break;
|
|
default:
|
|
MIPS_DEBUG("unknown branch");
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
|
|
int search_pc)
|
|
{
|
|
DisasContext ctx, *ctxp = &ctx;
|
|
target_ulong pc_start;
|
|
uint16_t *gen_opc_end;
|
|
int j, lj = -1;
|
|
|
|
pc_start = tb->pc;
|
|
gen_opc_ptr = gen_opc_buf;
|
|
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
|
|
gen_opparam_ptr = gen_opparam_buf;
|
|
ctx.pc = pc_start;
|
|
ctx.tb = tb;
|
|
ctx.bstate = BS_NONE;
|
|
/* Restore delay slot state */
|
|
ctx.hflags = env->hflags;
|
|
ctx.saved_hflags = ctx.hflags;
|
|
if (ctx.hflags & MIPS_HFLAG_BR) {
|
|
gen_op_restore_breg_target();
|
|
} else if (ctx.hflags & MIPS_HFLAG_B) {
|
|
ctx.btarget = env->btarget;
|
|
} else if (ctx.hflags & MIPS_HFLAG_BMASK) {
|
|
/* If we are in the delay slot of a conditional branch,
|
|
* restore the branch condition from env->bcond to T2
|
|
*/
|
|
ctx.btarget = env->btarget;
|
|
gen_op_restore_bcond();
|
|
}
|
|
#if defined(CONFIG_USER_ONLY)
|
|
ctx.mem_idx = 0;
|
|
#else
|
|
ctx.mem_idx = (ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM ? 0 : 1;
|
|
#endif
|
|
ctx.CP0_Status = env->CP0_Status;
|
|
#ifdef DEBUG_DISAS
|
|
if (loglevel & CPU_LOG_TB_CPU) {
|
|
fprintf(logfile, "------------------------------------------------\n");
|
|
cpu_dump_state(env, logfile, fprintf, 0);
|
|
}
|
|
#endif
|
|
#if defined MIPS_DEBUG_DISAS
|
|
if (loglevel & CPU_LOG_TB_IN_ASM)
|
|
fprintf(logfile, "\ntb %p super %d cond %04x %04x\n",
|
|
tb, ctx.mem_idx, ctx.hflags, env->hflags);
|
|
#endif
|
|
while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
|
|
if (search_pc) {
|
|
j = gen_opc_ptr - gen_opc_buf;
|
|
save_cpu_state(ctxp, 1);
|
|
if (lj < j) {
|
|
lj++;
|
|
while (lj < j)
|
|
gen_opc_instr_start[lj++] = 0;
|
|
gen_opc_pc[lj] = ctx.pc;
|
|
gen_opc_instr_start[lj] = 1;
|
|
}
|
|
}
|
|
ctx.opcode = ldl_code(ctx.pc);
|
|
decode_opc(&ctx);
|
|
ctx.pc += 4;
|
|
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
|
|
break;
|
|
#if defined (MIPS_SINGLE_STEP)
|
|
break;
|
|
#endif
|
|
}
|
|
if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) {
|
|
save_cpu_state(ctxp, 0);
|
|
gen_op_branch((long)ctx.tb, ctx.pc);
|
|
}
|
|
gen_op_reset_T0();
|
|
/* Generate the return instruction */
|
|
gen_op_exit_tb();
|
|
*gen_opc_ptr = INDEX_op_end;
|
|
if (search_pc) {
|
|
j = gen_opc_ptr - gen_opc_buf;
|
|
lj++;
|
|
while (lj <= j)
|
|
gen_opc_instr_start[lj++] = 0;
|
|
tb->size = 0;
|
|
} else {
|
|
tb->size = ctx.pc - pc_start;
|
|
}
|
|
#ifdef DEBUG_DISAS
|
|
#if defined MIPS_DEBUG_DISAS
|
|
if (loglevel & CPU_LOG_TB_IN_ASM)
|
|
fprintf(logfile, "\n");
|
|
#endif
|
|
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
|
target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
|
|
fprintf(logfile, "\n");
|
|
}
|
|
if (loglevel & CPU_LOG_TB_OP) {
|
|
fprintf(logfile, "OP:\n");
|
|
dump_ops(gen_opc_buf, gen_opparam_buf);
|
|
fprintf(logfile, "\n");
|
|
}
|
|
if (loglevel & CPU_LOG_TB_CPU) {
|
|
fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
|
|
{
|
|
return gen_intermediate_code_internal(env, tb, 0);
|
|
}
|
|
|
|
int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
|
|
{
|
|
return gen_intermediate_code_internal(env, tb, 1);
|
|
}
|
|
|
|
void cpu_dump_state (CPUState *env, FILE *f,
|
|
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
|
|
int flags)
|
|
{
|
|
int i;
|
|
|
|
cpu_fprintf(f, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
|
|
env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
|
|
for (i = 0; i < 32; i++) {
|
|
if ((i & 3) == 0)
|
|
cpu_fprintf(f, "GPR%02d:", i);
|
|
cpu_fprintf(f, " %s %08x", regnames[i], env->gpr[i]);
|
|
if ((i & 3) == 3)
|
|
cpu_fprintf(f, "\n");
|
|
}
|
|
cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x%08x\n",
|
|
env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
|
|
cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n",
|
|
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
|
|
}
|
|
|
|
CPUMIPSState *cpu_mips_init (void)
|
|
{
|
|
CPUMIPSState *env;
|
|
|
|
cpu_exec_init();
|
|
env = qemu_mallocz(sizeof(CPUMIPSState));
|
|
if (!env)
|
|
return NULL;
|
|
tlb_flush(env, 1);
|
|
/* Minimal init */
|
|
env->PC = 0xBFC00000;
|
|
#if defined (MIPS_USES_R4K_TLB)
|
|
env->CP0_random = MIPS_TLB_NB - 1;
|
|
#endif
|
|
env->CP0_Wired = 0;
|
|
env->CP0_Config0 = MIPS_CONFIG0;
|
|
#if defined (MIPS_CONFIG1)
|
|
env->CP0_Config1 = MIPS_CONFIG1;
|
|
#endif
|
|
#if defined (MIPS_CONFIG2)
|
|
env->CP0_Config2 = MIPS_CONFIG2;
|
|
#endif
|
|
#if defined (MIPS_CONFIG3)
|
|
env->CP0_Config3 = MIPS_CONFIG3;
|
|
#endif
|
|
env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
|
|
env->CP0_WatchLo = 0;
|
|
env->hflags = MIPS_HFLAG_ERL;
|
|
/* Count register increments in debug mode, EJTAG version 1 */
|
|
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
|
|
env->CP0_PRid = MIPS_CPU;
|
|
env->exception_index = EXCP_NONE;
|
|
|
|
cpu_single_env = env;
|
|
|
|
return env;
|
|
}
|