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dffdaf6162
On real hardware the ppc hash page table is stored in memory; accordingly our mmu emulation code can read a hash page table in guest memory. But, when paravirtualized under PAPR, the real hash page table is in host memory, accessible to the guest only via hypercalls. We model this by also allowing the MMU emulation code to access a specially allocated hash page table outside the guest's memory image. At present these two options are implemented with some ugly conditionals at each access point in the mmu emulation code. In the implementation of the PAPR hypercalls, we assume the external hash table. This patch cleans things up by adding helpers to load and store from the hash table for both 32-bit and 64-bit hash mmus. The 64-bit versions handle both the in-guest-memory and outside guest memory cases. The 32-bit versions only handle the in-guest-memory case since no 32-bit systems can have an external hash table at present. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
#if !defined (__MMU_HASH32_H__)
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#define __MMU_HASH32_H__
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#ifndef CONFIG_USER_ONLY
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hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash);
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hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
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int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
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int mmu_idx);
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/*
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* Segment register definitions
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*/
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#define SR32_T 0x80000000
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#define SR32_KS 0x40000000
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#define SR32_KP 0x20000000
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#define SR32_NX 0x10000000
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#define SR32_VSID 0x00ffffff
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/*
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* Block Address Translation (BAT) definitions
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*/
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#define BATU32_BEPIU 0xf0000000
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#define BATU32_BEPIL 0x0ffe0000
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#define BATU32_BEPI 0xfffe0000
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#define BATU32_BL 0x00001ffc
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#define BATU32_VS 0x00000002
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#define BATU32_VP 0x00000001
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#define BATL32_BRPNU 0xf0000000
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#define BATL32_BRPNL 0x0ffe0000
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#define BATL32_BRPN 0xfffe0000
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#define BATL32_WIMG 0x00000078
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#define BATL32_PP 0x00000003
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/* PowerPC 601 has slightly different BAT registers */
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#define BATU32_601_KS 0x00000008
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#define BATU32_601_KP 0x00000004
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#define BATU32_601_PP 0x00000003
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#define BATL32_601_V 0x00000040
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#define BATL32_601_BL 0x0000003f
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/*
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* Hash page table definitions
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*/
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#define HPTES_PER_GROUP 8
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#define HASH_PTE_SIZE_32 8
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#define HASH_PTEG_SIZE_32 (HASH_PTE_SIZE_32 * HPTES_PER_GROUP)
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#define HPTE32_V_VALID 0x80000000
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#define HPTE32_V_VSID 0x7fffff80
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#define HPTE32_V_SECONDARY 0x00000040
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#define HPTE32_V_API 0x0000003f
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#define HPTE32_V_COMPARE(x, y) (!(((x) ^ (y)) & 0x7fffffbf))
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#define HPTE32_R_RPN 0xfffff000
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#define HPTE32_R_R 0x00000100
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#define HPTE32_R_C 0x00000080
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#define HPTE32_R_W 0x00000040
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#define HPTE32_R_I 0x00000020
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#define HPTE32_R_M 0x00000010
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#define HPTE32_R_G 0x00000008
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#define HPTE32_R_WIMG 0x00000078
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#define HPTE32_R_PP 0x00000003
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static inline target_ulong ppc_hash32_load_hpte0(CPUPPCState *env,
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hwaddr pte_offset)
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{
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assert(!env->external_htab); /* Not supported on 32-bit for now */
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return ldl_phys(env->htab_base + pte_offset);
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}
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static inline target_ulong ppc_hash32_load_hpte1(CPUPPCState *env,
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hwaddr pte_offset)
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{
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assert(!env->external_htab); /* Not supported on 32-bit for now */
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return ldl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2);
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}
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static inline void ppc_hash32_store_hpte0(CPUPPCState *env,
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hwaddr pte_offset, target_ulong pte0)
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{
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assert(!env->external_htab); /* Not supported on 32-bit for now */
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stl_phys(env->htab_base + pte_offset, pte0);
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}
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static inline void ppc_hash32_store_hpte1(CPUPPCState *env,
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hwaddr pte_offset, target_ulong pte1)
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{
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assert(!env->external_htab); /* Not supported on 32-bit for now */
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stl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1);
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}
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#endif /* CONFIG_USER_ONLY */
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#endif /* __MMU_HASH32_H__ */
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