xemu/target-arm
Fabian Aggeler e389be1673 target-arm: implement PD0/PD1 bits for TTBCR
Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions).

Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and
get_level1_table_address.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Message-id: 1402409556-18574-1-git-send-email-aggelerf@ethz.ch
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-19 18:06:24 +01:00
..
2014-06-05 16:10:33 +02:00
2014-05-27 17:09:51 +01:00
2014-02-26 17:20:00 +00:00
2011-07-23 11:26:12 -05:00
2014-06-05 16:10:33 +02:00