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39bffca203
This was done in a mostly automated fashion. I did it in three steps and then rebased it into a single step which avoids repeatedly touching every file in the tree. The first step was a sed-based addition of the parent type to the subclass registration functions. The second step was another sed-based removal of subclass registration functions while also adding virtual functions from the base class into a class_init function as appropriate. Finally, a python script was used to convert the DeviceInfo structures and qdev_register_subclass functions to TypeInfo structures, class_init functions, and type_register_static calls. We are almost fully converted to QOM after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
166 lines
4.6 KiB
C
166 lines
4.6 KiB
C
/*
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* QEMU Intel 82374 emulation (Enhanced DMA controller)
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*
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* Copyright (c) 2010 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "isa.h"
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//#define DEBUG_I82374
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#ifdef DEBUG_I82374
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "i82374: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do {} while (0)
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#endif
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "i82374 ERROR: " fmt , ## __VA_ARGS__); } while (0)
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typedef struct I82374State {
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uint8_t commands[8];
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} I82374State;
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static const VMStateDescription vmstate_i82374 = {
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.name = "i82374",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8_ARRAY(commands, I82374State, 8),
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VMSTATE_END_OF_LIST()
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},
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};
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static uint32_t i82374_read_isr(void *opaque, uint32_t nport)
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{
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uint32_t val = 0;
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BADF("%s: %08x\n", __func__, nport);
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DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
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return val;
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}
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static void i82374_write_command(void *opaque, uint32_t nport, uint32_t data)
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{
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DPRINTF("%s: %08x=%08x\n", __func__, nport, data);
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if (data != 0x42) {
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/* Not Stop S/G command */
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BADF("%s: %08x=%08x\n", __func__, nport, data);
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}
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}
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static uint32_t i82374_read_status(void *opaque, uint32_t nport)
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{
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uint32_t val = 0;
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BADF("%s: %08x\n", __func__, nport);
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DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
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return val;
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}
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static void i82374_write_descriptor(void *opaque, uint32_t nport, uint32_t data)
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{
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DPRINTF("%s: %08x=%08x\n", __func__, nport, data);
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BADF("%s: %08x=%08x\n", __func__, nport, data);
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}
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static uint32_t i82374_read_descriptor(void *opaque, uint32_t nport)
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{
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uint32_t val = 0;
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BADF("%s: %08x\n", __func__, nport);
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DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
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return val;
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}
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static void i82374_init(I82374State *s)
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{
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DMA_init(1, NULL);
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memset(s->commands, 0, sizeof(s->commands));
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}
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typedef struct ISAi82374State {
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ISADevice dev;
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uint32_t iobase;
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I82374State state;
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} ISAi82374State;
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static const VMStateDescription vmstate_isa_i82374 = {
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.name = "isa-i82374",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT(state, ISAi82374State, 0, vmstate_i82374, I82374State),
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VMSTATE_END_OF_LIST()
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},
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};
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static int i82374_isa_init(ISADevice *dev)
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{
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ISAi82374State *isa = DO_UPCAST(ISAi82374State, dev, dev);
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I82374State *s = &isa->state;
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register_ioport_read(isa->iobase + 0x0A, 1, 1, i82374_read_isr, s);
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register_ioport_write(isa->iobase + 0x10, 8, 1, i82374_write_command, s);
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register_ioport_read(isa->iobase + 0x18, 8, 1, i82374_read_status, s);
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register_ioport_write(isa->iobase + 0x20, 0x20, 1, i82374_write_descriptor, s);
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register_ioport_read(isa->iobase + 0x20, 0x20, 1, i82374_read_descriptor, s);
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i82374_init(s);
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return 0;
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}
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static Property i82374_properties[] = {
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DEFINE_PROP_HEX32("iobase", ISAi82374State, iobase, 0x400),
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DEFINE_PROP_END_OF_LIST()
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};
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static void i82374_class_init(ObjectClass *klass, void *data)
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{
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ISADeviceClass *k = ISA_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->init = i82374_isa_init;
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dc->vmsd = &vmstate_isa_i82374;
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dc->props = i82374_properties;
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}
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static TypeInfo i82374_isa_info = {
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.name = "i82374",
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(ISAi82374State),
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.class_init = i82374_class_init,
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};
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static void i82374_register_devices(void)
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{
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type_register_static(&i82374_isa_info);
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}
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device_init(i82374_register_devices)
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