James Hogan e40df9a80b target/mips: Fix MIPS64 MFC0 UserLocal on BE host ...

Using MFC0 to read CP0_UserLocal uses tcg_gen_ld32s_tl, however
CP0_UserLocal is a target_ulong. On a big endian host with a MIPS64
target this reads and sign extends the more significant half of the
64-bit register.

Fix this by using ld_tl to load the whole target_ulong and ext32s_tl to
sign extend it, as done for various other target_ulong COP0 registers.

Fixes: d279279e2b5c ("target-mips: implement UserLocal Register")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>

2017-07-20 22:42:26 +01:00

..

cpu-qom.h

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cpu.c

qom/cpu: move tlb_flush to cpu_common_reset

2017-01-13 14:24:31 +00:00

cpu.h

target-mips: Provide function to test if a CPU supports an ISA

2017-02-21 22:24:58 +00:00

dsp_helper.c

…

gdbstub.c

…

helper.c

mips: set CP0 Debug DExcCode for SDBBP instruction

2017-07-17 16:48:21 +02:00

helper.h

target-mips: Use clz opcode

2017-01-10 08:06:11 -08:00

kvm_mips.h

…

kvm.c

vcpu_dirty: share the same field in CPUState for all accelerators

2017-07-04 14:30:03 +02:00

lmi_helper.c

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machine.c

migration: extend VMStateInfo

2017-01-24 17:54:47 +00:00

Makefile.objs

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mips-defs.h

…

mips-semi.c

…

msa_helper.c

…

op_helper.c

target/mips: hold BQL for timer interrupts

2017-03-09 10:41:48 +00:00

TODO

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trace-events

target-mips: replace few LOG_DISAS() with trace points

2017-03-20 11:06:32 +00:00

translate_init.c

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translate.c

target/mips: Fix MIPS64 MFC0 UserLocal on BE host

2017-07-20 22:42:26 +01:00