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Each PCI Bridge has a set of implied VGA regions that are enabled when the VGA bit is set in the bridge control register. This allows VGA devices behind bridges. Unfortunately with VGA Enable, which we formerly allowed but didn't back, comes along some required VGA baggage. VGA Palette Snooping is required, along with VGA 16-bit decoding. We don't yet have support for palette snooping. We also don't have support for 10-bit VGA aliases, the default mode, but we enable the register, even on root ports, to avoid confusing guests. Fortunately there's likely nothing from this century that requires these features, so the missing bits are noted with TODOs. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
82 lines
2.3 KiB
C
82 lines
2.3 KiB
C
#ifndef QEMU_PCI_BUS_H
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#define QEMU_PCI_BUS_H
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/*
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* PCI Bus and Bridge datastructures.
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*
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* Do not access the following members directly;
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* use accessor functions in pci.h, pci_bridge.h
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*/
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#define TYPE_PCI_BUS "PCI"
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#define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
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struct PCIBus {
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BusState qbus;
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PCIDMAContextFunc dma_context_fn;
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void *dma_context_opaque;
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uint8_t devfn_min;
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pci_set_irq_fn set_irq;
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pci_map_irq_fn map_irq;
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pci_route_irq_fn route_intx_to_irq;
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pci_hotplug_fn hotplug;
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DeviceState *hotplug_qdev;
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void *irq_opaque;
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PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
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PCIDevice *parent_dev;
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MemoryRegion *address_space_mem;
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MemoryRegion *address_space_io;
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QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
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QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int *irq_count;
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};
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typedef struct PCIBridgeWindows PCIBridgeWindows;
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/*
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* Aliases for each of the address space windows that the bridge
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* can forward. Mapped into the bridge's parent's address space,
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* as subregions.
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*/
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struct PCIBridgeWindows {
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MemoryRegion alias_pref_mem;
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MemoryRegion alias_mem;
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MemoryRegion alias_io;
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/*
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* When bridge control VGA forwarding is enabled, bridges will
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* provide positive decode on the PCI VGA defined I/O port and
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* MMIO ranges. When enabled forwarding is only qualified on the
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* I/O and memory enable bits in the bridge command register.
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*/
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MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS];
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};
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struct PCIBridge {
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PCIDevice dev;
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/* private member */
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PCIBus sec_bus;
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/*
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* Memory regions for the bridge's address spaces. These regions are not
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* directly added to system_memory/system_io or its descendants.
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* Bridge's secondary bus points to these, so that devices
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* under the bridge see these regions as its address spaces.
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* The regions are as large as the entire address space -
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* they don't take into account any windows.
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*/
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MemoryRegion address_space_mem;
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MemoryRegion address_space_io;
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PCIBridgeWindows *windows;
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pci_map_irq_fn map_irq;
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const char *bus_name;
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};
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#endif /* QEMU_PCI_BUS_H */
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