Palmer Dabbelt 3502dc824a RISC-V: Respect fences for user-only emulators ... Our current fence implementation ignores fences for the user-only configurations. This is incorrect but unlikely to manifest: it requires multi-threaded user-only code that takes advantage of the weakness in the host's memory model and can be inlined by TCG. This patch simply treats fences the same way for all our emulators. I've given it to testing as I don't want to construct a test that would actually trigger the failure. Our fence implementation has an additional deficiency where we map all RISC-V fences to full fences. Now that we have a formal memory model for RISC-V we can start to take advantage of the strength bits on our fence instructions. This requires a bit more though, so I'm going to split it out because the implementation is still correct without taking advantage of these weaker fences. Thanks to Richard Henderson for pointing out both of the issues. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>		2018-11-13 15:12:15 -08:00
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cpu_bits.h	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
cpu_helper.c	RISC-V: Move non-ops from op_helper to cpu_helper	2018-10-17 13:02:14 -07:00
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
cpu.c	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
cpu.h	RISC-V: Allow setting and clearing multiple irqs	2018-10-17 13:02:09 -07:00
fpu_helper.c	target/riscv: Remove floatX_maybe_silence_nan from conversions	2018-05-17 15:27:15 -07:00
gdbstub.c	RISC-V GDB Stub	2018-03-07 08:30:28 +13:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	RISC-V: Move non-ops from op_helper to cpu_helper	2018-10-17 13:02:14 -07:00
op_helper.c	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
pmp.c	target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64	2018-10-30 11:04:28 -07:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	RISC-V: Respect fences for user-only emulators	2018-11-13 15:12:15 -08:00