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ee640c625e
msix_init() reports errors with error_report(), which is wrong when
it's used in realize(). The same issue was fixed for msi_init() in
commit 1108b2f. In order to make the API change as small as possible,
leave the return value check to later patch.
For some devices(like e1000e, vmxnet3, nvme) who won't fail because of
msix_init's failure, suppress the error report by passing NULL error
object.
Bonus: add comment for msix_init.
CC: Jiri Pirko <jiri@resnulli.us>
CC: Gerd Hoffmann <kraxel@redhat.com>
CC: Dmitry Fleytman <dmitry@daynix.com>
CC: Jason Wang <jasowang@redhat.com>
CC: Michael S. Tsirkin <mst@redhat.com>
CC: Hannes Reinecke <hare@suse.de>
CC: Paolo Bonzini <pbonzini@redhat.com>
CC: Alex Williamson <alex.williamson@redhat.com>
CC: Markus Armbruster <armbru@redhat.com>
CC: Marcel Apfelbaum <marcel@redhat.com>
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
/*
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* Generic PCI Express Root Port emulation
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*
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* Copyright (C) 2017 Red Hat Inc
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*
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* Authors:
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/pci/msix.h"
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#include "hw/pci/pcie_port.h"
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#define TYPE_GEN_PCIE_ROOT_PORT "pcie-root-port"
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#define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100
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#define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1
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static uint8_t gen_rp_aer_vector(const PCIDevice *d)
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{
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return 0;
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}
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static int gen_rp_interrupts_init(PCIDevice *d, Error **errp)
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{
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int rc;
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rc = msix_init_exclusive_bar(d, GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR, 0, errp);
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if (rc < 0) {
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assert(rc == -ENOTSUP);
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} else {
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msix_vector_use(d, 0);
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}
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return rc;
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}
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static void gen_rp_interrupts_uninit(PCIDevice *d)
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{
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msix_uninit_exclusive_bar(d);
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}
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static const VMStateDescription vmstate_rp_dev = {
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.name = "pcie-root-port",
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = pcie_cap_slot_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
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VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
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PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
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VMSTATE_END_OF_LIST()
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}
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};
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static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
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k->vendor_id = PCI_VENDOR_ID_REDHAT;
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k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
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dc->desc = "PCI Express Root Port";
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dc->vmsd = &vmstate_rp_dev;
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rpc->aer_vector = gen_rp_aer_vector;
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rpc->interrupts_init = gen_rp_interrupts_init;
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rpc->interrupts_uninit = gen_rp_interrupts_uninit;
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rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
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}
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static const TypeInfo gen_rp_dev_info = {
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.name = TYPE_GEN_PCIE_ROOT_PORT,
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.parent = TYPE_PCIE_ROOT_PORT,
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.class_init = gen_rp_dev_class_init,
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};
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static void gen_rp_register_types(void)
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{
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type_register_static(&gen_rp_dev_info);
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}
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type_init(gen_rp_register_types)
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