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b89de436ff
Add a model of Xilinx Versal SoC. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20181102131913.1535-2-edgar.iglesias@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
324 lines
11 KiB
C
324 lines
11 KiB
C
/*
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* Xilinx Versal SoC model.
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*
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* Copyright (c) 2018 Xilinx Inc.
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* Written by Edgar E. Iglesias
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "qemu/log.h"
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#include "hw/sysbus.h"
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#include "net/net.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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#include "hw/arm/arm.h"
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#include "kvm_arm.h"
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#include "hw/misc/unimp.h"
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#include "hw/intc/arm_gicv3_common.h"
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#include "hw/arm/xlnx-versal.h"
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#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
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#define GEM_REVISION 0x40070106
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static void versal_create_apu_cpus(Versal *s)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
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Object *obj;
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char *name;
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obj = object_new(XLNX_VERSAL_ACPU_TYPE);
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if (!obj) {
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/* Secondary CPUs start in PSCI powered-down state */
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error_report("Unable to create apu.cpu[%d] of type %s",
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i, XLNX_VERSAL_ACPU_TYPE);
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exit(EXIT_FAILURE);
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}
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name = g_strdup_printf("apu-cpu[%d]", i);
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object_property_add_child(OBJECT(s), name, obj, &error_fatal);
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g_free(name);
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object_property_set_int(obj, s->cfg.psci_conduit,
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"psci-conduit", &error_abort);
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if (i) {
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object_property_set_bool(obj, true,
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"start-powered-off", &error_abort);
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}
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object_property_set_int(obj, ARRAY_SIZE(s->fpd.apu.cpu),
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"core-count", &error_abort);
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object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
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&error_abort);
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object_property_set_bool(obj, true, "realized", &error_fatal);
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s->fpd.apu.cpu[i] = ARM_CPU(obj);
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}
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}
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static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
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{
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static const uint64_t addrs[] = {
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MM_GIC_APU_DIST_MAIN,
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MM_GIC_APU_REDIST_0
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};
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SysBusDevice *gicbusdev;
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DeviceState *gicdev;
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int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);
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int i;
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sysbus_init_child_obj(OBJECT(s), "apu-gic",
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&s->fpd.apu.gic, sizeof(s->fpd.apu.gic),
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gicv3_class_name());
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gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);
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gicdev = DEVICE(&s->fpd.apu.gic);
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qdev_prop_set_uint32(gicdev, "revision", 3);
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qdev_prop_set_uint32(gicdev, "num-cpu", 2);
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qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32);
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qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
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qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2);
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qdev_prop_set_bit(gicdev, "has-security-extensions", true);
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object_property_set_bool(OBJECT(&s->fpd.apu.gic), true, "realized",
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&error_fatal);
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for (i = 0; i < ARRAY_SIZE(addrs); i++) {
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MemoryRegion *mr;
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mr = sysbus_mmio_get_region(gicbusdev, i);
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memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr);
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}
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for (i = 0; i < nr_apu_cpus; i++) {
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DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]);
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int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
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qemu_irq maint_irq;
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int ti;
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/* Mapping from the output timer irq lines from the CPU to the
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* GIC PPI inputs.
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*/
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const int timer_irq[] = {
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[GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ,
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[GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ,
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[GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ,
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[GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ,
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};
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for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) {
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qdev_connect_gpio_out(cpudev, ti,
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qdev_get_gpio_in(gicdev,
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ppibase + timer_irq[ti]));
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}
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maint_irq = qdev_get_gpio_in(gicdev,
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ppibase + VERSAL_GIC_MAINT_IRQ);
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qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
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0, maint_irq);
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sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
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sysbus_connect_irq(gicbusdev, i + nr_apu_cpus,
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qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
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sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus,
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qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
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sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus,
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qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
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}
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for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) {
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pic[i] = qdev_get_gpio_in(gicdev, i);
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}
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}
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static void versal_create_uarts(Versal *s, qemu_irq *pic)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
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static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0};
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static const uint64_t addrs[] = { MM_UART0, MM_UART1 };
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char *name = g_strdup_printf("uart%d", i);
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DeviceState *dev;
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MemoryRegion *mr;
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dev = qdev_create(NULL, "pl011");
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s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);
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qdev_prop_set_chr(dev, "chardev", serial_hd(i));
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object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
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qdev_init_nofail(dev);
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mr = sysbus_mmio_get_region(s->lpd.iou.uart[i], 0);
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memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
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sysbus_connect_irq(s->lpd.iou.uart[i], 0, pic[irqs[i]]);
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g_free(name);
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}
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}
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static void versal_create_gems(Versal *s, qemu_irq *pic)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
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static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0};
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static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 };
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char *name = g_strdup_printf("gem%d", i);
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NICInfo *nd = &nd_table[i];
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DeviceState *dev;
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MemoryRegion *mr;
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dev = qdev_create(NULL, "cadence_gem");
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s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev);
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object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
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if (nd->used) {
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qemu_check_nic_model(nd, "cadence_gem");
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qdev_set_nic_properties(dev, nd);
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}
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object_property_set_int(OBJECT(s->lpd.iou.gem[i]),
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2, "num-priority-queues",
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&error_abort);
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object_property_set_link(OBJECT(s->lpd.iou.gem[i]),
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OBJECT(&s->mr_ps), "dma",
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&error_abort);
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qdev_init_nofail(dev);
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mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0);
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memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
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sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]);
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g_free(name);
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}
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}
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/* This takes the board allocated linear DDR memory and creates aliases
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* for each split DDR range/aperture on the Versal address map.
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*/
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static void versal_map_ddr(Versal *s)
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{
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uint64_t size = memory_region_size(s->cfg.mr_ddr);
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/* Describes the various split DDR access regions. */
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static const struct {
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uint64_t base;
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uint64_t size;
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} addr_ranges[] = {
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{ MM_TOP_DDR, MM_TOP_DDR_SIZE },
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{ MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
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{ MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
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{ MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
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};
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uint64_t offset = 0;
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int i;
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assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges));
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for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
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char *name;
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uint64_t mapsize;
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mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
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name = g_strdup_printf("noc-ddr-range%d", i);
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/* Create the MR alias. */
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memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s),
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name, s->cfg.mr_ddr,
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offset, mapsize);
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/* Map it onto the NoC MR. */
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memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base,
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&s->noc.mr_ddr_ranges[i]);
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offset += mapsize;
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size -= mapsize;
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g_free(name);
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}
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}
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static void versal_unimp_area(Versal *s, const char *name,
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MemoryRegion *mr,
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hwaddr base, hwaddr size)
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{
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DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
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MemoryRegion *mr_dev;
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qdev_prop_set_string(dev, "name", name);
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qdev_prop_set_uint64(dev, "size", size);
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object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
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qdev_init_nofail(dev);
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mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
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memory_region_add_subregion(mr, base, mr_dev);
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}
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static void versal_unimp(Versal *s)
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{
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versal_unimp_area(s, "psm", &s->mr_ps,
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MM_PSM_START, MM_PSM_END - MM_PSM_START);
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versal_unimp_area(s, "crl", &s->mr_ps,
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MM_CRL, MM_CRL_SIZE);
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versal_unimp_area(s, "crf", &s->mr_ps,
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MM_FPD_CRF, MM_FPD_CRF_SIZE);
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versal_unimp_area(s, "iou-scntr", &s->mr_ps,
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MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
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versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
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MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE);
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}
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static void versal_realize(DeviceState *dev, Error **errp)
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{
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Versal *s = XLNX_VERSAL(dev);
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qemu_irq pic[XLNX_VERSAL_NR_IRQS];
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versal_create_apu_cpus(s);
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versal_create_apu_gic(s, pic);
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versal_create_uarts(s, pic);
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versal_create_gems(s, pic);
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versal_map_ddr(s);
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versal_unimp(s);
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/* Create the On Chip Memory (OCM). */
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memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm",
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MM_OCM_SIZE, &error_fatal);
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memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
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memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
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}
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static void versal_init(Object *obj)
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{
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Versal *s = XLNX_VERSAL(obj);
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memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
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memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
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}
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static Property versal_properties[] = {
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DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_UINT32("psci-conduit", Versal, cfg.psci_conduit, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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static void versal_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = versal_realize;
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dc->props = versal_properties;
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/* No VMSD since we haven't got any top-level SoC state to save. */
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}
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static const TypeInfo versal_info = {
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.name = TYPE_XLNX_VERSAL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Versal),
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.instance_init = versal_init,
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.class_init = versal_class_init,
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};
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static void versal_register_types(void)
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{
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type_register_static(&versal_info);
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}
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type_init(versal_register_types);
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