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It's either "GNU *Library* General Public License version 2" or "GNU Lesser General Public License version *2.1*", but there was no "version 2.0" of the "Lesser" license. So assume that version 2.1 is meant here. Acked-by: Stafford Horne <shorne@gmail.com> Message-Id: <1550073577-4248-1-git-send-email-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
190 lines
6.4 KiB
Plaintext
190 lines
6.4 KiB
Plaintext
#
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# OpenRISC instruction decode definitions.
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#
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# Copyright (c) 2018 Richard Henderson <rth@twiddle.net>
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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&dab d a b
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&da d a
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&ab a b
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&dal d a l
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&ai a i
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####
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# System Instructions
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####
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l_sys 001000 0000000000 k:16
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l_trap 001000 0100000000 k:16
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l_msync 001000 1000000000 00000000 00000000
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l_psync 001000 1010000000 00000000 00000000
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l_csync 001000 1100000000 00000000 00000000
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l_rfe 001001 ----- ----- -------- --------
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####
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# Branch Instructions
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####
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l_j 000000 n:s26
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l_jal 000001 n:s26
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l_bnf 000011 n:s26
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l_bf 000100 n:s26
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l_jr 010001 ---------- b:5 -----------
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l_jalr 010010 ---------- b:5 -----------
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####
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# Memory Instructions
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####
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&load d a i
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@load ...... d:5 a:5 i:s16 &load
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%store_i 21:s5 0:11
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&store a b i
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@store ...... ..... a:5 b:5 ........... &store i=%store_i
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l_lwa 011011 ..... ..... ........ ........ @load
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l_lwz 100001 ..... ..... ........ ........ @load
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l_lws 100010 ..... ..... ........ ........ @load
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l_lbz 100011 ..... ..... ........ ........ @load
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l_lbs 100100 ..... ..... ........ ........ @load
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l_lhz 100101 ..... ..... ........ ........ @load
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l_lhs 100110 ..... ..... ........ ........ @load
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l_swa 110011 ..... ..... ..... ........... @store
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l_sw 110101 ..... ..... ..... ........... @store
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l_sb 110110 ..... ..... ..... ........... @store
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l_sh 110111 ..... ..... ..... ........... @store
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####
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# Immediate Operand Instructions
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####
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%mtspr_k 21:5 0:11
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&rri d a i
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&rrk d a k
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@rri ...... d:5 a:5 i:s16 &rri
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@rrk ...... d:5 a:5 k:16 &rrk
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l_nop 000101 01--- ----- k:16
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l_addi 100111 ..... ..... ........ ........ @rri
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l_addic 101000 ..... ..... ........ ........ @rri
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l_andi 101001 ..... ..... ........ ........ @rrk
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l_ori 101010 ..... ..... ........ ........ @rrk
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l_xori 101011 ..... ..... ........ ........ @rri
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l_muli 101100 ..... ..... ........ ........ @rri
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l_mfspr 101101 ..... ..... ........ ........ @rrk
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l_mtspr 110000 ..... a:5 b:5 ........... k=%mtspr_k
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l_maci 010011 ----- a:5 i:s16
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l_movhi 000110 d:5 ----0 k:16
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l_macrc 000110 d:5 ----1 00000000 00000000
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####
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# Arithmetic Instructions
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####
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l_exths 111000 d:5 a:5 ----- - 0000 -- 1100
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l_extbs 111000 d:5 a:5 ----- - 0001 -- 1100
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l_exthz 111000 d:5 a:5 ----- - 0010 -- 1100
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l_extbz 111000 d:5 a:5 ----- - 0011 -- 1100
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l_add 111000 d:5 a:5 b:5 - 00 ---- 0000
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l_addc 111000 d:5 a:5 b:5 - 00 ---- 0001
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l_sub 111000 d:5 a:5 b:5 - 00 ---- 0010
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l_and 111000 d:5 a:5 b:5 - 00 ---- 0011
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l_or 111000 d:5 a:5 b:5 - 00 ---- 0100
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l_xor 111000 d:5 a:5 b:5 - 00 ---- 0101
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l_cmov 111000 d:5 a:5 b:5 - 00 ---- 1110
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l_ff1 111000 d:5 a:5 ----- - 00 ---- 1111
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l_fl1 111000 d:5 a:5 ----- - 01 ---- 1111
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l_sll 111000 d:5 a:5 b:5 - 0000 -- 1000
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l_srl 111000 d:5 a:5 b:5 - 0001 -- 1000
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l_sra 111000 d:5 a:5 b:5 - 0010 -- 1000
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l_ror 111000 d:5 a:5 b:5 - 0011 -- 1000
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l_mul 111000 d:5 a:5 b:5 - 11 ---- 0110
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l_mulu 111000 d:5 a:5 b:5 - 11 ---- 1011
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l_div 111000 d:5 a:5 b:5 - 11 ---- 1001
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l_divu 111000 d:5 a:5 b:5 - 11 ---- 1010
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l_muld 111000 ----- a:5 b:5 - 11 ---- 0111
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l_muldu 111000 ----- a:5 b:5 - 11 ---- 1100
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l_mac 110001 ----- a:5 b:5 ------- 0001
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l_macu 110001 ----- a:5 b:5 ------- 0011
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l_msb 110001 ----- a:5 b:5 ------- 0010
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l_msbu 110001 ----- a:5 b:5 ------- 0100
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l_slli 101110 d:5 a:5 -------- 00 l:6
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l_srli 101110 d:5 a:5 -------- 01 l:6
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l_srai 101110 d:5 a:5 -------- 10 l:6
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l_rori 101110 d:5 a:5 -------- 11 l:6
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####
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# Compare Instructions
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####
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l_sfeq 111001 00000 a:5 b:5 -----------
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l_sfne 111001 00001 a:5 b:5 -----------
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l_sfgtu 111001 00010 a:5 b:5 -----------
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l_sfgeu 111001 00011 a:5 b:5 -----------
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l_sfltu 111001 00100 a:5 b:5 -----------
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l_sfleu 111001 00101 a:5 b:5 -----------
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l_sfgts 111001 01010 a:5 b:5 -----------
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l_sfges 111001 01011 a:5 b:5 -----------
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l_sflts 111001 01100 a:5 b:5 -----------
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l_sfles 111001 01101 a:5 b:5 -----------
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l_sfeqi 101111 00000 a:5 i:s16
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l_sfnei 101111 00001 a:5 i:s16
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l_sfgtui 101111 00010 a:5 i:s16
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l_sfgeui 101111 00011 a:5 i:s16
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l_sfltui 101111 00100 a:5 i:s16
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l_sfleui 101111 00101 a:5 i:s16
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l_sfgtsi 101111 01010 a:5 i:s16
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l_sfgesi 101111 01011 a:5 i:s16
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l_sfltsi 101111 01100 a:5 i:s16
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l_sflesi 101111 01101 a:5 i:s16
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####
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# FP Instructions
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####
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lf_add_s 110010 d:5 a:5 b:5 --- 00000000
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lf_sub_s 110010 d:5 a:5 b:5 --- 00000001
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lf_mul_s 110010 d:5 a:5 b:5 --- 00000010
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lf_div_s 110010 d:5 a:5 b:5 --- 00000011
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lf_rem_s 110010 d:5 a:5 b:5 --- 00000110
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lf_madd_s 110010 d:5 a:5 b:5 --- 00000111
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lf_itof_s 110010 d:5 a:5 00000 --- 00000100
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lf_ftoi_s 110010 d:5 a:5 00000 --- 00000101
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lf_sfeq_s 110010 ----- a:5 b:5 --- 00001000
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lf_sfne_s 110010 ----- a:5 b:5 --- 00001001
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lf_sfgt_s 110010 ----- a:5 b:5 --- 00001010
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lf_sfge_s 110010 ----- a:5 b:5 --- 00001011
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lf_sflt_s 110010 ----- a:5 b:5 --- 00001100
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lf_sfle_s 110010 ----- a:5 b:5 --- 00001101
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