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8dbe22c686
Let's introduce RAM_NORESERVE, allowing mmap'ing with MAP_NORESERVE. The new flag has the following semantics: " RAM is mmap-ed with MAP_NORESERVE. When set, reserving swap space (or huge pages if applicable) is skipped: will bail out if not supported. When not set, the OS will do the reservation, if supported for the memory type. " Allow passing it into: - memory_region_init_ram_nomigrate() - memory_region_init_resizeable_ram() - memory_region_init_ram_from_file() ... and teach qemu_ram_mmap() and qemu_anon_ram_alloc() about the flag. Bail out if the flag is not supported, which is the case right now for both, POSIX and win32. We will add Linux support next and allow specifying RAM_NORESERVE via memory backends. The target use case is virtio-mem, which dynamically exposes memory inside a large, sparse memory area to the VM. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com> for memory backend and machine core Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210510114328.21835-9-david@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
114 lines
3.6 KiB
C
114 lines
3.6 KiB
C
#ifndef CPU_COMMON_H
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#define CPU_COMMON_H
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/* CPU interfaces that are target independent. */
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#ifndef CONFIG_USER_ONLY
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#include "exec/hwaddr.h"
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#endif
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/* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */
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void qemu_init_cpu_list(void);
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void cpu_list_lock(void);
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void cpu_list_unlock(void);
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void tcg_flush_softmmu_tlb(CPUState *cs);
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void tcg_iommu_init_notifier_list(CPUState *cpu);
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void tcg_iommu_free_notifier_list(CPUState *cpu);
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#if !defined(CONFIG_USER_ONLY)
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enum device_endian {
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DEVICE_NATIVE_ENDIAN,
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DEVICE_BIG_ENDIAN,
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DEVICE_LITTLE_ENDIAN,
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};
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#if defined(HOST_WORDS_BIGENDIAN)
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#define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
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#else
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#define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
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#endif
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/* address in the RAM (different from a physical address) */
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#if defined(CONFIG_XEN_BACKEND)
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typedef uint64_t ram_addr_t;
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# define RAM_ADDR_MAX UINT64_MAX
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# define RAM_ADDR_FMT "%" PRIx64
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#else
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typedef uintptr_t ram_addr_t;
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# define RAM_ADDR_MAX UINTPTR_MAX
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# define RAM_ADDR_FMT "%" PRIxPTR
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#endif
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/* memory API */
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void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
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/* This should not be used by devices. */
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ram_addr_t qemu_ram_addr_from_host(void *ptr);
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RAMBlock *qemu_ram_block_by_name(const char *name);
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RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
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ram_addr_t *offset);
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ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host);
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void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
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void qemu_ram_unset_idstr(RAMBlock *block);
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const char *qemu_ram_get_idstr(RAMBlock *rb);
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void *qemu_ram_get_host_addr(RAMBlock *rb);
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ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
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ram_addr_t qemu_ram_get_used_length(RAMBlock *rb);
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ram_addr_t qemu_ram_get_max_length(RAMBlock *rb);
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bool qemu_ram_is_shared(RAMBlock *rb);
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bool qemu_ram_is_noreserve(RAMBlock *rb);
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bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
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void qemu_ram_set_uf_zeroable(RAMBlock *rb);
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bool qemu_ram_is_migratable(RAMBlock *rb);
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void qemu_ram_set_migratable(RAMBlock *rb);
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void qemu_ram_unset_migratable(RAMBlock *rb);
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size_t qemu_ram_pagesize(RAMBlock *block);
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size_t qemu_ram_pagesize_largest(void);
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void cpu_physical_memory_rw(hwaddr addr, void *buf,
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hwaddr len, bool is_write);
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static inline void cpu_physical_memory_read(hwaddr addr,
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void *buf, hwaddr len)
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{
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cpu_physical_memory_rw(addr, buf, len, false);
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}
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static inline void cpu_physical_memory_write(hwaddr addr,
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const void *buf, hwaddr len)
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{
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cpu_physical_memory_rw(addr, (void *)buf, len, true);
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}
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void *cpu_physical_memory_map(hwaddr addr,
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hwaddr *plen,
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bool is_write);
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void cpu_physical_memory_unmap(void *buffer, hwaddr len,
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bool is_write, hwaddr access_len);
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void cpu_register_map_client(QEMUBH *bh);
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void cpu_unregister_map_client(QEMUBH *bh);
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bool cpu_physical_memory_is_io(hwaddr phys_addr);
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/* Coalesced MMIO regions are areas where write operations can be reordered.
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* This usually implies that write operations are side-effect free. This allows
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* batching which can make a major impact on performance when using
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* virtualization.
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*/
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void qemu_flush_coalesced_mmio_buffer(void);
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void cpu_flush_icache_range(hwaddr start, hwaddr len);
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typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque);
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int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
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int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
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#endif
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/* vl.c */
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extern int singlestep;
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#endif /* CPU_COMMON_H */
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