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The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54 RISC-V cores. Currently the sifive_u machine only populates 4 U54 cores. Update the max cpu number to 5 to reflect the real hardware, by creating 2 CPU clusters as containers for RISC-V hart arrays to populate heterogeneous harts. The cpu nodes in the generated DTS have been updated as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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.. | ||
boot.c | ||
Kconfig | ||
Makefile.objs | ||
riscv_hart.c | ||
riscv_htif.c | ||
sifive_clint.c | ||
sifive_e_prci.c | ||
sifive_e.c | ||
sifive_gpio.c | ||
sifive_plic.c | ||
sifive_test.c | ||
sifive_u.c | ||
sifive_uart.c | ||
spike.c | ||
trace-events | ||
virt.c |