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ee4402eae1
-----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAluQU38ACgkQIeENKd+X cFRAXQgAlhNcwby+Jsk8sbLajMWXEtww9FIv+XESldPOJHmJyCkNDVZX8MuMM7+f 8NraD3YGDJvXP/BEcmyE5yPC6mx+OIi8ufzqP0rUML1x4+Tpxp8nZ7sBH197RtGg eImPA6oKvg4wyfNOrZ+hGa8HF/iMT03TqeKggUPf3dVAs8LV2iUwBIzrRLB4IhIN yFnhbcw8cW04tWUhYg4+viDY2k0q7fMrJZkASD/RjGMBjubJkwWvSYOdMIEWSpcG 2qLT5SohzUzHyKPONsoBKjSIP+nKgtyYR6IJh40FDd5S5RRMHe/n3q9jChIkHMma x1eSNvVd41++QlBKqDeAlA+gbdK/uw== =FJn/ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-pullreq-20180905' into staging A misc collection of RISC-V related patches for 3.1. # gpg: Signature made Wed 05 Sep 2018 23:06:55 BST # gpg: using RSA key 21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-pullreq-20180905: riscv: remove define cpu_init() hw/riscv/spike: Set the soc device tree node as a simple-bus hw/riscv/virtio: Set the soc device tree node as a simple-bus target/riscv: call gen_goto_tb on DISAS_TOO_MANY target/riscv: optimize indirect branches target/riscv: optimize cross-page direct jumps in softmmu RISC-V: Simplify riscv_cpu_local_irqs_pending RISC-V: Use atomic_cmpxchg to update PLIC bitmaps RISC-V: Improve page table walker spec compliance RISC-V: Update address bits to support sv39 and sv48 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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