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bf1b52d199
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023121649.19123-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
321 lines
8.9 KiB
C
321 lines
8.9 KiB
C
/*
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* CRIS helper routines.
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*
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* Copyright (c) 2007 AXIS Communications AB
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* Written by Edgar E. Iglesias.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "mmu.h"
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#include "qemu/host-utils.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "exec/helper-proto.h"
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//#define CRIS_HELPER_DEBUG
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#ifdef CRIS_HELPER_DEBUG
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#define D(x) x
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#define D_LOG(...) qemu_log(__VA_ARGS__)
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#else
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#define D(x)
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#define D_LOG(...) do { } while (0)
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#endif
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#if defined(CONFIG_USER_ONLY)
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void cris_cpu_do_interrupt(CPUState *cs)
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{
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CRISCPU *cpu = CRIS_CPU(cs);
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CPUCRISState *env = &cpu->env;
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cs->exception_index = -1;
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env->pregs[PR_ERP] = env->pc;
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}
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void crisv10_cpu_do_interrupt(CPUState *cs)
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{
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cris_cpu_do_interrupt(cs);
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}
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bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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CRISCPU *cpu = CRIS_CPU(cs);
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cs->exception_index = 0xaa;
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cpu->env.pregs[PR_EDA] = address;
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cpu_loop_exit_restore(cs, retaddr);
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}
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#else /* !CONFIG_USER_ONLY */
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static void cris_shift_ccs(CPUCRISState *env)
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{
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uint32_t ccs;
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/* Apply the ccs shift. */
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ccs = env->pregs[PR_CCS];
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ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
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env->pregs[PR_CCS] = ccs;
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}
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bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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CRISCPU *cpu = CRIS_CPU(cs);
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CPUCRISState *env = &cpu->env;
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struct cris_mmu_result res;
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int prot, miss;
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target_ulong phy;
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miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
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access_type, mmu_idx, 0);
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if (likely(!miss)) {
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/*
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* Mask off the cache selection bit. The ETRAX busses do not
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* see the top bit.
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*/
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phy = res.phy & ~0x80000000;
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prot = res.prot;
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tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
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prot, mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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if (probe) {
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return false;
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}
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if (cs->exception_index == EXCP_BUSFAULT) {
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cpu_abort(cs, "CRIS: Illegal recursive bus fault."
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"addr=%" VADDR_PRIx " access_type=%d\n",
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address, access_type);
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}
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env->pregs[PR_EDA] = address;
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cs->exception_index = EXCP_BUSFAULT;
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env->fault_vector = res.bf_vec;
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if (retaddr) {
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if (cpu_restore_state(cs, retaddr, true)) {
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/* Evaluate flags after retranslation. */
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helper_top_evaluate_flags(env);
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}
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}
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cpu_loop_exit(cs);
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}
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void crisv10_cpu_do_interrupt(CPUState *cs)
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{
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CRISCPU *cpu = CRIS_CPU(cs);
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CPUCRISState *env = &cpu->env;
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int ex_vec = -1;
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D_LOG("exception index=%d interrupt_req=%d\n",
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cs->exception_index,
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cs->interrupt_request);
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if (env->dslot) {
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/* CRISv10 never takes interrupts while in a delay-slot. */
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cpu_abort(cs, "CRIS: Interrupt on delay-slot\n");
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}
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assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
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switch (cs->exception_index) {
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case EXCP_BREAK:
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/* These exceptions are genereated by the core itself.
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ERP should point to the insn following the brk. */
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ex_vec = env->trap_vector;
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env->pregs[PRV10_BRP] = env->pc;
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break;
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case EXCP_NMI:
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/* NMI is hardwired to vector zero. */
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ex_vec = 0;
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env->pregs[PR_CCS] &= ~M_FLAG_V10;
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env->pregs[PRV10_BRP] = env->pc;
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break;
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case EXCP_BUSFAULT:
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cpu_abort(cs, "Unhandled busfault");
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break;
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default:
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/* The interrupt controller gives us the vector. */
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ex_vec = env->interrupt_vector;
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/* Normal interrupts are taken between
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TB's. env->pc is valid here. */
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env->pregs[PR_ERP] = env->pc;
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break;
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}
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if (env->pregs[PR_CCS] & U_FLAG) {
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/* Swap stack pointers. */
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env->pregs[PR_USP] = env->regs[R_SP];
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env->regs[R_SP] = env->ksp;
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}
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/* Now that we are in kernel mode, load the handlers address. */
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env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
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env->locked_irq = 1;
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env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
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qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
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__func__, env->pc, ex_vec,
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env->pregs[PR_CCS],
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env->pregs[PR_PID],
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env->pregs[PR_ERP]);
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}
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void cris_cpu_do_interrupt(CPUState *cs)
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{
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CRISCPU *cpu = CRIS_CPU(cs);
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CPUCRISState *env = &cpu->env;
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int ex_vec = -1;
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D_LOG("exception index=%d interrupt_req=%d\n",
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cs->exception_index,
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cs->interrupt_request);
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switch (cs->exception_index) {
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case EXCP_BREAK:
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/* These exceptions are genereated by the core itself.
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ERP should point to the insn following the brk. */
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ex_vec = env->trap_vector;
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env->pregs[PR_ERP] = env->pc;
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break;
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case EXCP_NMI:
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/* NMI is hardwired to vector zero. */
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ex_vec = 0;
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env->pregs[PR_CCS] &= ~M_FLAG_V32;
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env->pregs[PR_NRP] = env->pc;
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break;
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case EXCP_BUSFAULT:
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ex_vec = env->fault_vector;
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env->pregs[PR_ERP] = env->pc;
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break;
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default:
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/* The interrupt controller gives us the vector. */
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ex_vec = env->interrupt_vector;
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/* Normal interrupts are taken between
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TB's. env->pc is valid here. */
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env->pregs[PR_ERP] = env->pc;
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break;
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}
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/* Fill in the IDX field. */
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env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
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if (env->dslot) {
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D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
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" ERP=%x pid=%x ccs=%x cc=%d %x\n",
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ex_vec, env->pc, env->dslot,
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env->regs[R_SP],
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env->pregs[PR_ERP], env->pregs[PR_PID],
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env->pregs[PR_CCS],
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env->cc_op, env->cc_mask);
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/* We loose the btarget, btaken state here so rexec the
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branch. */
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env->pregs[PR_ERP] -= env->dslot;
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/* Exception starts with dslot cleared. */
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env->dslot = 0;
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}
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if (env->pregs[PR_CCS] & U_FLAG) {
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/* Swap stack pointers. */
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env->pregs[PR_USP] = env->regs[R_SP];
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env->regs[R_SP] = env->ksp;
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}
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/* Apply the CRIS CCS shift. Clears U if set. */
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cris_shift_ccs(env);
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/* Now that we are in kernel mode, load the handlers address.
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This load may not fault, real hw leaves that behaviour as
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undefined. */
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env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
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/* Clear the excption_index to avoid spurios hw_aborts for recursive
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bus faults. */
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cs->exception_index = -1;
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D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
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__func__, env->pc, ex_vec,
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env->pregs[PR_CCS],
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env->pregs[PR_PID],
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env->pregs[PR_ERP]);
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}
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hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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CRISCPU *cpu = CRIS_CPU(cs);
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uint32_t phy = addr;
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struct cris_mmu_result res;
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int miss;
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miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1);
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/* If D TLB misses, try I TLB. */
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if (miss) {
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miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1);
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}
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if (!miss) {
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phy = res.phy;
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}
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D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
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return phy;
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}
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#endif
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bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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CPUClass *cc = CPU_GET_CLASS(cs);
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CRISCPU *cpu = CRIS_CPU(cs);
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CPUCRISState *env = &cpu->env;
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bool ret = false;
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if (interrupt_request & CPU_INTERRUPT_HARD
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&& (env->pregs[PR_CCS] & I_FLAG)
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&& !env->locked_irq) {
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cs->exception_index = EXCP_IRQ;
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cc->do_interrupt(cs);
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ret = true;
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}
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if (interrupt_request & CPU_INTERRUPT_NMI) {
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unsigned int m_flag_archval;
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if (env->pregs[PR_VR] < 32) {
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m_flag_archval = M_FLAG_V10;
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} else {
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m_flag_archval = M_FLAG_V32;
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}
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if ((env->pregs[PR_CCS] & m_flag_archval)) {
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cs->exception_index = EXCP_NMI;
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cc->do_interrupt(cs);
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ret = true;
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}
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}
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return ret;
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}
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