xemu/target/ppc
Mark Cave-Ayland ef96e3ae96 target/ppc: move FP and VMX registers into aligned vsr register array
The VSX register array is a block of 64 128-bit registers where the first 32
registers consist of the existing 64-bit FP registers extended to 128-bit
using new VSR registers, and the last 32 registers are the VMX 128-bit
registers as show below:

            64-bit               64-bit
    +--------------------+--------------------+
    |        FP0         |                    |  VSR0
    +--------------------+--------------------+
    |        FP1         |                    |  VSR1
    +--------------------+--------------------+
    |        ...         |        ...         |  ...
    +--------------------+--------------------+
    |        FP30        |                    |  VSR30
    +--------------------+--------------------+
    |        FP31        |                    |  VSR31
    +--------------------+--------------------+
    |                  VMX0                   |  VSR32
    +-----------------------------------------+
    |                  VMX1                   |  VSR33
    +-----------------------------------------+
    |                  ...                    |  ...
    +-----------------------------------------+
    |                  VMX30                  |  VSR62
    +-----------------------------------------+
    |                  VMX31                  |  VSR63
    +-----------------------------------------+

In order to allow for future conversion of VSX instructions to use TCG vector
operations, recreate the same layout using an aligned version of the existing
vsr register array.

Since the old fpr and avr register arrays are removed, the existing callers
must also be updated to use the correct offset in the vsr register array. This
also includes switching the relevant VMState fields over to using subarrays
to make sure that migration is preserved.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09 09:28:14 +11:00
..
translate target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
arch_dump.c target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
compat.c target/ppc: Allow cpu compatiblity checks based on type, not instance 2018-06-21 21:22:53 +10:00
cpu-models.c target/ppc/cpu-models: Re-group the 970 CPUs together again 2018-09-25 11:12:25 +10:00
cpu-models.h target/ppc: Add POWER9 DD2.0 model information 2017-10-17 10:34:00 +11:00
cpu-qom.h ppc: Remove deprecated ppcemb target 2018-08-28 11:31:23 +10:00
cpu.c target/ppc: support for 32-bit carry and overflow 2017-03-01 11:23:39 +11:00
cpu.h target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
dfp_helper.c
excp_helper.c ppc: add DBCR based debugging 2018-08-21 14:28:45 +10:00
fpu_helper.c target/ppc: Split out float_invalid_cvt 2018-11-08 12:04:40 +11:00
gdbstub.c target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
helper_regs.h target/ppc: Include "exec/exec-all.h" which provides tlb_flush() 2018-05-31 19:12:13 +02:00
helper.h target/ppc: add external PID support 2018-11-08 12:04:40 +11:00
int_helper.c target/ppc: merge ppc_vsr_t and ppc_avr_t union types 2019-01-09 09:28:14 +11:00
internal.h target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
kvm_ppc.h ppc/spapr_caps: Add SPAPR_CAP_NESTED_KVM_HV 2018-11-08 13:08:35 +11:00
kvm-stub.c openpic: move KVM-specific declarations into separate openpic_kvm.h file 2018-03-06 13:16:29 +11:00
kvm.c target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
machine.c target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
Makefile.objs build: remove CONFIG_LIBDECNUMBER 2017-10-16 18:03:52 +02:00
mem_helper.c target/ppc: add external PID support 2018-11-08 12:04:40 +11:00
mfrom_table_gen.c
mfrom_table.inc.c rename included C files to foo.inc.c, remove osdep.h 2018-05-11 14:33:40 +02:00
misc_helper.c target/ppc: Allow privileged access to SPR_PCR 2018-06-12 09:33:52 +10:00
mmu_helper.c target/ppc: add external PID support 2018-11-08 12:04:40 +11:00
mmu-book3s-v3.c Include qapi/error.h exactly where needed 2018-02-09 13:50:17 +01:00
mmu-book3s-v3.h target/ppc: add basic support for PTCR on POWER9 2018-05-04 09:56:27 +10:00
mmu-hash32.c target/ppc: Eliminate htab_base and htab_mask variables 2017-03-01 11:23:39 +11:00
mmu-hash32.h target/ppc: Manage external HPT via virtual hypervisor 2017-03-01 11:23:39 +11:00
mmu-hash64.c target/ppc: Add ppc_hash64_filter_pagesizes() 2018-06-22 14:19:07 +10:00
mmu-hash64.h target/ppc: Add ppc_hash64_filter_pagesizes() 2018-06-22 14:19:07 +10:00
mmu-radix64.c Include qapi/error.h exactly where needed 2018-02-09 13:50:17 +01:00
mmu-radix64.h target/ppc: Add debug function for radix mmu translation 2017-07-11 11:04:02 +10:00
monitor.c target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
timebase_helper.c
trace-events docs: fix broken paths to docs/devel/tracing.txt 2017-07-31 13:12:53 +03:00
translate_init.inc.c target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
translate.c target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
user_only_helper.c accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00