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6a22895908
Augment the GIC's QOM device interface by adding two new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to each CPU. We never use these, but it's helpful to keep the v2-and-earlier GIC's external interface in line with that of the GICv3 to avoid board code having to add extra code conditional on which version of the GIC is in use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1483977924-14522-3-git-send-email-peter.maydell@linaro.org
140 lines
4.7 KiB
C
140 lines
4.7 KiB
C
/*
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* ARM GIC support
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*
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* Copyright (c) 2012 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_ARM_GIC_COMMON_H
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#define HW_ARM_GIC_COMMON_H
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#include "hw/sysbus.h"
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/* Maximum number of possible interrupts, determined by the GIC architecture */
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#define GIC_MAXIRQ 1020
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/* First 32 are private to each CPU (SGIs and PPIs). */
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#define GIC_INTERNAL 32
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#define GIC_NR_SGIS 16
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/* Maximum number of possible CPU interfaces, determined by GIC architecture */
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#define GIC_NCPU 8
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#define MAX_NR_GROUP_PRIO 128
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#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
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#define GIC_MIN_BPR 0
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#define GIC_MIN_ABPR (GIC_MIN_BPR + 1)
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typedef struct gic_irq_state {
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/* The enable bits are only banked for per-cpu interrupts. */
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uint8_t enabled;
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uint8_t pending;
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uint8_t active;
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uint8_t level;
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bool model; /* 0 = N:N, 1 = 1:N */
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bool edge_trigger; /* true: edge-triggered, false: level-triggered */
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uint8_t group;
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} gic_irq_state;
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typedef struct GICState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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qemu_irq parent_irq[GIC_NCPU];
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qemu_irq parent_fiq[GIC_NCPU];
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qemu_irq parent_virq[GIC_NCPU];
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qemu_irq parent_vfiq[GIC_NCPU];
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/* GICD_CTLR; for a GIC with the security extensions the NS banked version
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* of this register is just an alias of bit 1 of the S banked version.
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*/
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uint32_t ctlr;
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/* GICC_CTLR; again, the NS banked version is just aliases of bits of
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* the S banked register, so our state only needs to store the S version.
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*/
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uint32_t cpu_ctlr[GIC_NCPU];
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gic_irq_state irq_state[GIC_MAXIRQ];
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uint8_t irq_target[GIC_MAXIRQ];
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uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
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uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
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/* For each SGI on the target CPU, we store 8 bits
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* indicating which source CPUs have made this SGI
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* pending on the target CPU. These correspond to
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* the bytes in the GIC_SPENDSGIR* registers as
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* read by the target CPU.
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*/
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uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
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uint16_t priority_mask[GIC_NCPU];
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uint16_t running_priority[GIC_NCPU];
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uint16_t current_pending[GIC_NCPU];
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/* If we present the GICv2 without security extensions to a guest,
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* the guest can configure the GICC_CTLR to configure group 1 binary point
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* in the abpr.
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* For a GIC with Security Extensions we use use bpr for the
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* secure copy and abpr as storage for the non-secure copy of the register.
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*/
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uint8_t bpr[GIC_NCPU];
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uint8_t abpr[GIC_NCPU];
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/* The APR is implementation defined, so we choose a layout identical to
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* the KVM ABI layout for QEMU's implementation of the gic:
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* If an interrupt for preemption level X is active, then
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* APRn[X mod 32] == 0b1, where n = X / 32
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* otherwise the bit is clear.
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*/
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uint32_t apr[GIC_NR_APRS][GIC_NCPU];
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uint32_t nsapr[GIC_NR_APRS][GIC_NCPU];
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uint32_t num_cpu;
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MemoryRegion iomem; /* Distributor */
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/* This is just so we can have an opaque pointer which identifies
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* both this GIC and which CPU interface we should be accessing.
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*/
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struct GICState *backref[GIC_NCPU];
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MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
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uint32_t num_irq;
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uint32_t revision;
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bool security_extn;
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bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? */
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int dev_fd; /* kvm device fd if backed by kvm vgic support */
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Error *migration_blocker;
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} GICState;
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#define TYPE_ARM_GIC_COMMON "arm_gic_common"
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#define ARM_GIC_COMMON(obj) \
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OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
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#define ARM_GIC_COMMON_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
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#define ARM_GIC_COMMON_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
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typedef struct ARMGICCommonClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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/*< public >*/
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void (*pre_save)(GICState *s);
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void (*post_load)(GICState *s);
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} ARMGICCommonClass;
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void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
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const MemoryRegionOps *ops);
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#endif
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