mirror of
https://github.com/xemu-project/xemu.git
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4771d756f4
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
379 lines
14 KiB
C
379 lines
14 KiB
C
/*
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* Samsung exynos4210 SoC emulation
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
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* Maksim Kozlov <m.kozlov@samsung.com>
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* Evgeny Voevodin <e.voevodin@samsung.com>
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* Igor Mitsyanko <i.mitsyanko@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/boards.h"
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#include "sysemu/sysemu.h"
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#include "hw/sysbus.h"
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#include "hw/arm/arm.h"
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#include "hw/loader.h"
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#include "hw/arm/exynos4210.h"
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#include "hw/usb/hcd-ehci.h"
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#define EXYNOS4210_CHIPID_ADDR 0x10000000
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/* PWM */
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#define EXYNOS4210_PWM_BASE_ADDR 0x139D0000
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/* RTC */
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#define EXYNOS4210_RTC_BASE_ADDR 0x10070000
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/* MCT */
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#define EXYNOS4210_MCT_BASE_ADDR 0x10050000
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/* I2C */
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#define EXYNOS4210_I2C_SHIFT 0x00010000
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#define EXYNOS4210_I2C_BASE_ADDR 0x13860000
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/* Interrupt Group of External Interrupt Combiner for I2C */
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#define EXYNOS4210_I2C_INTG 27
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#define EXYNOS4210_HDMI_INTG 16
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/* UART's definitions */
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#define EXYNOS4210_UART0_BASE_ADDR 0x13800000
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#define EXYNOS4210_UART1_BASE_ADDR 0x13810000
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#define EXYNOS4210_UART2_BASE_ADDR 0x13820000
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#define EXYNOS4210_UART3_BASE_ADDR 0x13830000
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#define EXYNOS4210_UART0_FIFO_SIZE 256
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#define EXYNOS4210_UART1_FIFO_SIZE 64
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#define EXYNOS4210_UART2_FIFO_SIZE 16
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#define EXYNOS4210_UART3_FIFO_SIZE 16
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/* Interrupt Group of External Interrupt Combiner for UART */
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#define EXYNOS4210_UART_INT_GRP 26
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/* External GIC */
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#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000
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#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000
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/* Combiner */
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#define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000
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#define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000
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/* PMU SFR base address */
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#define EXYNOS4210_PMU_BASE_ADDR 0x10020000
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/* Display controllers (FIMD) */
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#define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000
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/* EHCI */
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#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
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static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
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0x09, 0x00, 0x00, 0x00 };
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static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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assert(offset < sizeof(chipid_and_omr));
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return chipid_and_omr[offset];
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}
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static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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return;
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}
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static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
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.read = exynos4210_chipid_and_omr_read,
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.write = exynos4210_chipid_and_omr_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.max_access_size = 1,
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}
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};
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void exynos4210_write_secondary(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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int n;
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uint32_t smpboot[] = {
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0xe59f3034, /* ldr r3, External gic_cpu_if */
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0xe59f2034, /* ldr r2, Internal gic_cpu_if */
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0xe59f0034, /* ldr r0, startaddr */
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0xe3a01001, /* mov r1, #1 */
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0xe5821000, /* str r1, [r2] */
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0xe5831000, /* str r1, [r3] */
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0xe3a010ff, /* mov r1, #0xff */
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0xe5821004, /* str r1, [r2, #4] */
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0xe5831004, /* str r1, [r3, #4] */
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0xf57ff04f, /* dsb */
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0xe320f003, /* wfi */
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0xe5901000, /* ldr r1, [r0] */
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0xe1110001, /* tst r1, r1 */
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0x0afffffb, /* beq <wfi> */
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0xe12fff11, /* bx r1 */
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EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
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0, /* gic_cpu_if: base address of Internal GIC CPU interface */
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0 /* bootreg: Boot register address is held here */
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};
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smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
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smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
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for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
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smpboot[n] = tswap32(smpboot[n]);
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}
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rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
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info->smp_loader_start);
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}
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Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
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unsigned long ram_size)
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{
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int i, n;
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Exynos4210State *s = g_new(Exynos4210State, 1);
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qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
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unsigned long mem_size;
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DeviceState *dev;
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SysBusDevice *busdev;
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ObjectClass *cpu_oc;
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cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
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assert(cpu_oc);
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for (n = 0; n < EXYNOS4210_NCPUS; n++) {
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Object *cpuobj = object_new(object_class_get_name(cpu_oc));
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/* By default A9 CPUs have EL3 enabled. This board does not currently
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* support EL3 so the CPU EL3 property is disabled before realization.
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*/
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if (object_property_find(cpuobj, "has_el3", NULL)) {
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object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
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}
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s->cpu[n] = ARM_CPU(cpuobj);
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object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
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"reset-cbar", &error_abort);
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object_property_set_bool(cpuobj, true, "realized", &error_fatal);
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}
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/*** IRQs ***/
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s->irq_table = exynos4210_init_irq(&s->irqs);
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/* IRQ Gate */
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for (i = 0; i < EXYNOS4210_NCPUS; i++) {
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dev = qdev_create(NULL, "exynos4210.irq_gate");
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qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
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qdev_init_nofail(dev);
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/* Get IRQ Gate input in gate_irq */
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for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
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gate_irq[i][n] = qdev_get_gpio_in(dev, n);
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}
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busdev = SYS_BUS_DEVICE(dev);
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/* Connect IRQ Gate output to CPU's IRQ line */
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sysbus_connect_irq(busdev, 0,
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qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
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}
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/* Private memory region and Internal GIC */
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dev = qdev_create(NULL, "a9mpcore_priv");
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qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
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for (n = 0; n < EXYNOS4210_NCPUS; n++) {
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sysbus_connect_irq(busdev, n, gate_irq[n][0]);
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}
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for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
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s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
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}
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/* Cache controller */
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sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
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/* External GIC */
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dev = qdev_create(NULL, "exynos4210.gic");
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qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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/* Map CPU interface */
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sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
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/* Map Distributer interface */
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sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
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for (n = 0; n < EXYNOS4210_NCPUS; n++) {
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sysbus_connect_irq(busdev, n, gate_irq[n][1]);
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}
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for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
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s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
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}
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/* Internal Interrupt Combiner */
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dev = qdev_create(NULL, "exynos4210.combiner");
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
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sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
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}
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exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
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sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
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/* External Interrupt Combiner */
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dev = qdev_create(NULL, "exynos4210.combiner");
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qdev_prop_set_uint32(dev, "external", 1);
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
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sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
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}
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exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
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sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
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/* Initialize board IRQs. */
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exynos4210_init_board_irqs(&s->irqs);
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/*** Memory ***/
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/* Chip-ID and OMR */
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memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops,
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NULL, "exynos4210.chipid", sizeof(chipid_and_omr));
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memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
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&s->chipid_mem);
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/* Internal ROM */
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memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom",
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EXYNOS4210_IROM_SIZE, &error_fatal);
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vmstate_register_ram_global(&s->irom_mem);
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memory_region_set_readonly(&s->irom_mem, true);
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memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
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&s->irom_mem);
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/* mirror of iROM */
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memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias",
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&s->irom_mem,
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0,
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EXYNOS4210_IROM_SIZE);
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memory_region_set_readonly(&s->irom_alias_mem, true);
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memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
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&s->irom_alias_mem);
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/* Internal RAM */
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memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
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EXYNOS4210_IRAM_SIZE, &error_fatal);
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vmstate_register_ram_global(&s->iram_mem);
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memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
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&s->iram_mem);
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/* DRAM */
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mem_size = ram_size;
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if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
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memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
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mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal);
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vmstate_register_ram_global(&s->dram1_mem);
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memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
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&s->dram1_mem);
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mem_size = EXYNOS4210_DRAM_MAX_SIZE;
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}
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memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
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&error_fatal);
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vmstate_register_ram_global(&s->dram0_mem);
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memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
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&s->dram0_mem);
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/* PMU.
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* The only reason of existence at the moment is that secondary CPU boot
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* loader uses PMU INFORM5 register as a holding pen.
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*/
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sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
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/* PWM */
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sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
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s->irq_table[exynos4210_get_irq(22, 0)],
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s->irq_table[exynos4210_get_irq(22, 1)],
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s->irq_table[exynos4210_get_irq(22, 2)],
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s->irq_table[exynos4210_get_irq(22, 3)],
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s->irq_table[exynos4210_get_irq(22, 4)],
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NULL);
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/* RTC */
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sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
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s->irq_table[exynos4210_get_irq(23, 0)],
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s->irq_table[exynos4210_get_irq(23, 1)],
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NULL);
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/* Multi Core Timer */
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dev = qdev_create(NULL, "exynos4210.mct");
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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for (n = 0; n < 4; n++) {
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/* Connect global timer interrupts to Combiner gpio_in */
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sysbus_connect_irq(busdev, n,
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s->irq_table[exynos4210_get_irq(1, 4 + n)]);
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}
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/* Connect local timer interrupts to Combiner gpio_in */
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sysbus_connect_irq(busdev, 4,
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s->irq_table[exynos4210_get_irq(51, 0)]);
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sysbus_connect_irq(busdev, 5,
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s->irq_table[exynos4210_get_irq(35, 3)]);
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sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
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/*** I2C ***/
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for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
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uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
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qemu_irq i2c_irq;
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if (n < 8) {
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i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
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} else {
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i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
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}
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dev = qdev_create(NULL, "exynos4210.i2c");
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_connect_irq(busdev, 0, i2c_irq);
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sysbus_mmio_map(busdev, 0, addr);
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s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
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}
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/*** UARTs ***/
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exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
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EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
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s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
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exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
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EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
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s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
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exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
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EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
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s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
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exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
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EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
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s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
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/*** Display controller (FIMD) ***/
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sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
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s->irq_table[exynos4210_get_irq(11, 0)],
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s->irq_table[exynos4210_get_irq(11, 1)],
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s->irq_table[exynos4210_get_irq(11, 2)],
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NULL);
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sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
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s->irq_table[exynos4210_get_irq(28, 3)]);
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return s;
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}
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