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f502cfc207
Implement handling for the AArch64 SP_EL0 system register. This holds the EL0 stack pointer, and is only accessible when it's not being used as the stack pointer, ie when we're in EL1 and EL1 is using its own stack pointer. We also provide a definition of the SP_EL1 register; this isn't guest visible as a system register for an implementation like QEMU which doesn't provide EL2 or EL3; however it is useful for ensuring the underlying state is migrated. We need to update the state fields in the CPU state whenever we switch stack pointers; this happens when we take an exception and also when SPSEL is used to change the bit in PSTATE which indicates which stack pointer EL1 should use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
452 lines
11 KiB
C
452 lines
11 KiB
C
/*
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* ARM helper routines
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*
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* Copyright (c) 2005-2007 CodeSourcery, LLC
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "helper.h"
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#include "internals.h"
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#define SIGNBIT (uint32_t)0x80000000
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#define SIGNBIT64 ((uint64_t)1 << 63)
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static void raise_exception(CPUARMState *env, int tt)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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cs->exception_index = tt;
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cpu_loop_exit(cs);
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}
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uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
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uint32_t rn, uint32_t maxindex)
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{
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uint32_t val;
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uint32_t tmp;
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int index;
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int shift;
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uint64_t *table;
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table = (uint64_t *)&env->vfp.regs[rn];
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val = 0;
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for (shift = 0; shift < 32; shift += 8) {
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index = (ireg >> shift) & 0xff;
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if (index < maxindex) {
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tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
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val |= tmp << shift;
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} else {
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val |= def & (0xff << shift);
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}
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}
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return val;
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}
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#if !defined(CONFIG_USER_ONLY)
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#include "exec/softmmu_exec.h"
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#define MMUSUFFIX _mmu
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#define SHIFT 0
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#include "exec/softmmu_template.h"
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#define SHIFT 1
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#include "exec/softmmu_template.h"
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#define SHIFT 2
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#include "exec/softmmu_template.h"
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#define SHIFT 3
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#include "exec/softmmu_template.h"
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/* try to fill the TLB and return an exception if error. If retaddr is
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* NULL, it means that the function was called in C code (i.e. not
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* from generated code or from helper.c)
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*/
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void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
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uintptr_t retaddr)
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{
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int ret;
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ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
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if (unlikely(ret)) {
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (retaddr) {
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/* now we have a real cpu fault */
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cpu_restore_state(cs, retaddr);
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}
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raise_exception(env, cs->exception_index);
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}
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}
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#endif
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uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a + b;
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if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
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env->QF = 1;
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return res;
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}
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uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a + b;
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if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
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env->QF = 1;
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res = ~(((int32_t)a >> 31) ^ SIGNBIT);
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}
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return res;
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}
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uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a - b;
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if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
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env->QF = 1;
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res = ~(((int32_t)a >> 31) ^ SIGNBIT);
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}
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return res;
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}
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uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
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{
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uint32_t res;
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if (val >= 0x40000000) {
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res = ~SIGNBIT;
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env->QF = 1;
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} else if (val <= (int32_t)0xc0000000) {
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res = SIGNBIT;
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env->QF = 1;
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} else {
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res = val << 1;
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}
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return res;
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}
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uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a + b;
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if (res < a) {
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env->QF = 1;
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res = ~0;
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}
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return res;
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}
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uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a - b;
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if (res > a) {
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env->QF = 1;
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res = 0;
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}
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return res;
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}
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/* Signed saturation. */
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static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
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{
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int32_t top;
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uint32_t mask;
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top = val >> shift;
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mask = (1u << shift) - 1;
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if (top > 0) {
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env->QF = 1;
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return mask;
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} else if (top < -1) {
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env->QF = 1;
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return ~mask;
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}
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return val;
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}
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/* Unsigned saturation. */
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static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
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{
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uint32_t max;
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max = (1u << shift) - 1;
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if (val < 0) {
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env->QF = 1;
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return 0;
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} else if (val > max) {
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env->QF = 1;
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return max;
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}
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return val;
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}
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/* Signed saturate. */
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uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
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{
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return do_ssat(env, x, shift);
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}
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/* Dual halfword signed saturate. */
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uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
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{
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uint32_t res;
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res = (uint16_t)do_ssat(env, (int16_t)x, shift);
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res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
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return res;
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}
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/* Unsigned saturate. */
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uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
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{
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return do_usat(env, x, shift);
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}
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/* Dual halfword unsigned saturate. */
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uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
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{
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uint32_t res;
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res = (uint16_t)do_usat(env, (int16_t)x, shift);
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res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
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return res;
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}
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void HELPER(wfi)(CPUARMState *env)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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cs->exception_index = EXCP_HLT;
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cs->halted = 1;
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cpu_loop_exit(cs);
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}
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void HELPER(wfe)(CPUARMState *env)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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/* Don't actually halt the CPU, just yield back to top
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* level loop
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*/
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cs->exception_index = EXCP_YIELD;
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cpu_loop_exit(cs);
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}
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/* Raise an internal-to-QEMU exception. This is limited to only
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* those EXCP values which are special cases for QEMU to interrupt
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* execution and not to be used for exceptions which are passed to
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* the guest (those must all have syndrome information and thus should
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* use exception_with_syndrome).
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*/
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void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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assert(excp_is_internal(excp));
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cs->exception_index = excp;
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cpu_loop_exit(cs);
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}
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/* Raise an exception with the specified syndrome register value */
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void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
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uint32_t syndrome)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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assert(!excp_is_internal(excp));
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cs->exception_index = excp;
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env->exception.syndrome = syndrome;
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cpu_loop_exit(cs);
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}
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uint32_t HELPER(cpsr_read)(CPUARMState *env)
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{
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return cpsr_read(env) & ~CPSR_EXEC;
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}
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void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
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{
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cpsr_write(env, val, mask);
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}
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/* Access to user mode registers from privileged modes. */
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uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
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{
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uint32_t val;
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if (regno == 13) {
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val = env->banked_r13[0];
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} else if (regno == 14) {
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val = env->banked_r14[0];
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} else if (regno >= 8
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&& (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
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val = env->usr_regs[regno - 8];
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} else {
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val = env->regs[regno];
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}
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return val;
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}
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void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
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{
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if (regno == 13) {
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env->banked_r13[0] = val;
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} else if (regno == 14) {
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env->banked_r14[0] = val;
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} else if (regno >= 8
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&& (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
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env->usr_regs[regno - 8] = val;
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} else {
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env->regs[regno] = val;
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}
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}
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void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome)
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{
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const ARMCPRegInfo *ri = rip;
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switch (ri->accessfn(env, ri)) {
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case CP_ACCESS_OK:
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return;
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case CP_ACCESS_TRAP:
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env->exception.syndrome = syndrome;
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break;
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case CP_ACCESS_TRAP_UNCATEGORIZED:
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env->exception.syndrome = syn_uncategorized();
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break;
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default:
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g_assert_not_reached();
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}
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raise_exception(env, EXCP_UDEF);
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}
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void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
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{
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const ARMCPRegInfo *ri = rip;
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ri->writefn(env, ri, value);
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}
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uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
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{
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const ARMCPRegInfo *ri = rip;
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return ri->readfn(env, ri);
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}
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void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
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{
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const ARMCPRegInfo *ri = rip;
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ri->writefn(env, ri, value);
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}
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uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
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{
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const ARMCPRegInfo *ri = rip;
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return ri->readfn(env, ri);
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}
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void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
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{
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/* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
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* Note that SPSel is never OK from EL0; we rely on handle_msr_i()
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* to catch that case at translate time.
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*/
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if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
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raise_exception(env, EXCP_UDEF);
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}
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switch (op) {
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case 0x05: /* SPSel */
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update_spsel(env, imm);
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break;
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case 0x1e: /* DAIFSet */
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env->daif |= (imm << 6) & PSTATE_DAIF;
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break;
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case 0x1f: /* DAIFClear */
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env->daif &= ~((imm << 6) & PSTATE_DAIF);
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break;
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default:
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g_assert_not_reached();
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}
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}
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/* ??? Flag setting arithmetic is awkward because we need to do comparisons.
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The only way to do that in TCG is a conditional branch, which clobbers
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all our temporaries. For now implement these as helper functions. */
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/* Similarly for variable shift instructions. */
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uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
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{
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int shift = i & 0xff;
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if (shift >= 32) {
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if (shift == 32)
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env->CF = x & 1;
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else
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env->CF = 0;
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return 0;
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} else if (shift != 0) {
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env->CF = (x >> (32 - shift)) & 1;
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return x << shift;
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}
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return x;
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}
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uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
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{
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int shift = i & 0xff;
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if (shift >= 32) {
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if (shift == 32)
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env->CF = (x >> 31) & 1;
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else
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env->CF = 0;
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return 0;
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} else if (shift != 0) {
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env->CF = (x >> (shift - 1)) & 1;
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return x >> shift;
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}
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return x;
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}
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uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
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{
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int shift = i & 0xff;
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if (shift >= 32) {
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env->CF = (x >> 31) & 1;
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return (int32_t)x >> 31;
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} else if (shift != 0) {
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env->CF = (x >> (shift - 1)) & 1;
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return (int32_t)x >> shift;
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}
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return x;
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}
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uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
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{
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int shift1, shift;
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shift1 = i & 0xff;
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shift = shift1 & 0x1f;
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if (shift == 0) {
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if (shift1 != 0)
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env->CF = (x >> 31) & 1;
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return x;
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} else {
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env->CF = (x >> (shift - 1)) & 1;
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return ((uint32_t)x >> shift) | (x << (32 - shift));
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}
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}
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