xemu/target
Roman Bolshakov ddd31732a7 i386: hvf: Reset IRQ inhibition after moving RIP
The sequence of instructions exposes an issue:
  sti
  hlt

Interrupts cannot be delivered to hvf after hlt instruction cpu because
HF_INHIBIT_IRQ_MASK is set just before hlt is handled and never reset
after moving instruction pointer beyond hlt.

So, after hvf_vcpu_exec() returns, CPU thread gets locked up forever in
qemu_wait_io_event() (cpu_thread_is_idle() evaluates inhibition
flag and considers the CPU idle if the flag is set).

Cc: Cameron Esfahani <dirty@apple.com>
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Message-Id: <20200328174411.51491-1-r.bolshakov@yadro.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-04-02 14:55:45 -04:00
..
alpha x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
arm target/arm: fix incorrect current EL bug in aarch32 exception emulation 2020-03-30 13:55:32 +01:00
cris x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
hppa x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
i386 i386: hvf: Reset IRQ inhibition after moving RIP 2020-04-02 14:55:45 -04:00
lm32 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
m68k x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
microblaze x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
mips target/mips: Fix loongson multimedia condition instructions 2020-03-28 14:09:45 -07:00
moxie cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
nios2 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
openrisc x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
ppc hw/ppc: Take QEMU lock when calling ppc_dcr_read/write() 2020-03-24 11:56:37 +11:00
riscv x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
rx target/rx: Dump bytes for each insn during disassembly 2020-03-19 17:58:05 +01:00
s390x x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
sh4 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
sparc x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
tilegx cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
tricore cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
unicore32 tcg: Search includes from the project root source directory 2020-01-15 15:13:10 -10:00
xtensa x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00