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d902ae7558
For a-profile aarch64, which does not bank system registers, it takes
quite a lot of code to switch between security states. In the process,
registers such as TCR_EL{1,2} must be swapped, which in itself requires
the flushing of softmmu tlbs. Therefore it doesn't buy us anything to
separate tlbs by security state.
Retain the distinction between Stage2 and Stage2_S.
This will be important as we implement FEAT_RME, and do not wish to
add a third set of mmu indexes for Realm state.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38 lines
782 B
C
38 lines
782 B
C
/*
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* ARM cpu parameters for qemu.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* SPDX-License-Identifier: LGPL-2.0+
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*/
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#ifndef ARM_CPU_PARAM_H
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#define ARM_CPU_PARAM_H
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#ifdef TARGET_AARCH64
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# define TARGET_LONG_BITS 64
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# define TARGET_PHYS_ADDR_SPACE_BITS 52
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# define TARGET_VIRT_ADDR_SPACE_BITS 52
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#else
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# define TARGET_LONG_BITS 32
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# define TARGET_PHYS_ADDR_SPACE_BITS 40
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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#endif
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#ifdef CONFIG_USER_ONLY
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#define TARGET_PAGE_BITS 12
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# ifdef TARGET_AARCH64
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# define TARGET_TAGGED_ADDRESSES
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# endif
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#else
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/*
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* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
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* have to support 1K tiny pages.
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*/
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# define TARGET_PAGE_BITS_VARY
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# define TARGET_PAGE_BITS_MIN 10
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#endif
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#define NB_MMU_MODES 8
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#endif
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