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fc1c8344e6
We passed an is_write flag to the fuzz_dma_read_cb function to differentiate between the mapped DMA regions that need to be populated with fuzzed data, and those that don't. We simply passed through the address_space_map is_write parameter. The goal was to cut down on unnecessarily populating mapped DMA regions, when they are not read from. Unfortunately, nothing precludes code from reading from regions mapped with is_write=true. For example, see: https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg04729.html This patch removes the is_write parameter to fuzz_dma_read_cb. As a result, we will fill all mapped DMA regions with fuzzed data, ignoring the specified transfer direction. Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Reviewed-by: Darren Kenny <darren.kenny@oracle.com> Message-Id: <20210120060255.558535-1-alxndr@bu.edu>
112 lines
3.8 KiB
C++
112 lines
3.8 KiB
C++
/*
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* Memory access templates for MemoryRegionCache
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*
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* Copyright (c) 2018 Red Hat, Inc.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#define ADDRESS_SPACE_LD_CACHED(size) \
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glue(glue(address_space_ld, size), glue(ENDIANNESS, _cached))
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#define ADDRESS_SPACE_LD_CACHED_SLOW(size) \
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glue(glue(address_space_ld, size), glue(ENDIANNESS, _cached_slow))
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#define LD_P(size) \
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glue(glue(ld, size), glue(ENDIANNESS, _p))
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static inline uint32_t ADDRESS_SPACE_LD_CACHED(l)(MemoryRegionCache *cache,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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assert(addr < cache->len && 4 <= cache->len - addr);
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fuzz_dma_read_cb(cache->xlat + addr, 4, cache->mrs.mr);
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if (likely(cache->ptr)) {
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return LD_P(l)(cache->ptr + addr);
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} else {
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return ADDRESS_SPACE_LD_CACHED_SLOW(l)(cache, addr, attrs, result);
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}
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}
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static inline uint64_t ADDRESS_SPACE_LD_CACHED(q)(MemoryRegionCache *cache,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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assert(addr < cache->len && 8 <= cache->len - addr);
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fuzz_dma_read_cb(cache->xlat + addr, 8, cache->mrs.mr);
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if (likely(cache->ptr)) {
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return LD_P(q)(cache->ptr + addr);
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} else {
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return ADDRESS_SPACE_LD_CACHED_SLOW(q)(cache, addr, attrs, result);
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}
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}
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static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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assert(addr < cache->len && 2 <= cache->len - addr);
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fuzz_dma_read_cb(cache->xlat + addr, 2, cache->mrs.mr);
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if (likely(cache->ptr)) {
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return LD_P(uw)(cache->ptr + addr);
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} else {
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return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result);
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}
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}
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#undef ADDRESS_SPACE_LD_CACHED
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#undef ADDRESS_SPACE_LD_CACHED_SLOW
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#undef LD_P
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#define ADDRESS_SPACE_ST_CACHED(size) \
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glue(glue(address_space_st, size), glue(ENDIANNESS, _cached))
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#define ADDRESS_SPACE_ST_CACHED_SLOW(size) \
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glue(glue(address_space_st, size), glue(ENDIANNESS, _cached_slow))
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#define ST_P(size) \
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glue(glue(st, size), glue(ENDIANNESS, _p))
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static inline void ADDRESS_SPACE_ST_CACHED(l)(MemoryRegionCache *cache,
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hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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assert(addr < cache->len && 4 <= cache->len - addr);
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if (likely(cache->ptr)) {
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ST_P(l)(cache->ptr + addr, val);
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} else {
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ADDRESS_SPACE_ST_CACHED_SLOW(l)(cache, addr, val, attrs, result);
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}
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}
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static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache,
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hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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assert(addr < cache->len && 2 <= cache->len - addr);
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if (likely(cache->ptr)) {
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ST_P(w)(cache->ptr + addr, val);
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} else {
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ADDRESS_SPACE_ST_CACHED_SLOW(w)(cache, addr, val, attrs, result);
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}
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}
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static inline void ADDRESS_SPACE_ST_CACHED(q)(MemoryRegionCache *cache,
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hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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assert(addr < cache->len && 8 <= cache->len - addr);
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if (likely(cache->ptr)) {
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ST_P(q)(cache->ptr + addr, val);
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} else {
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ADDRESS_SPACE_ST_CACHED_SLOW(q)(cache, addr, val, attrs, result);
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}
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}
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#undef ADDRESS_SPACE_ST_CACHED
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#undef ADDRESS_SPACE_ST_CACHED_SLOW
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#undef ST_P
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#undef ENDIANNESS
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