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42bb9c9178
The uint32_t *app argument doesn't exist in real hardware. It was a hack in xilinx_axidma/enet to fake the (secondary) control stream connection. Removed the argument and added the second stream to axienet/dma. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
97 lines
3.0 KiB
C
97 lines
3.0 KiB
C
#ifndef HW_XILINX_H
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#define HW_XILINX_H 1
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#include "qemu-common.h"
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#include "qapi/qmp/qerror.h"
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#include "hw/stream.h"
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#include "net/net.h"
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static inline DeviceState *
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xilinx_intc_create(hwaddr base, qemu_irq irq, int kind_of_intr)
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{
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DeviceState *dev;
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dev = qdev_create(NULL, "xlnx.xps-intc");
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qdev_prop_set_uint32(dev, "kind-of-intr", kind_of_intr);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
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return dev;
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}
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/* OPB Timer/Counter. */
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static inline DeviceState *
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xilinx_timer_create(hwaddr base, qemu_irq irq, int oto, int freq)
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{
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DeviceState *dev;
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dev = qdev_create(NULL, "xlnx.xps-timer");
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qdev_prop_set_uint32(dev, "one-timer-only", oto);
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qdev_prop_set_uint32(dev, "clock-frequency", freq);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
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return dev;
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}
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/* XPS Ethernet Lite MAC. */
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static inline DeviceState *
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xilinx_ethlite_create(NICInfo *nd, hwaddr base, qemu_irq irq,
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int txpingpong, int rxpingpong)
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{
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DeviceState *dev;
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qemu_check_nic_model(nd, "xlnx.xps-ethernetlite");
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dev = qdev_create(NULL, "xlnx.xps-ethernetlite");
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qdev_set_nic_properties(dev, nd);
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qdev_prop_set_uint32(dev, "tx-ping-pong", txpingpong);
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qdev_prop_set_uint32(dev, "rx-ping-pong", rxpingpong);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
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return dev;
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}
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static inline void
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xilinx_axiethernet_init(DeviceState *dev, NICInfo *nd, StreamSlave *ds,
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StreamSlave *cs, hwaddr base, qemu_irq irq, int txmem,
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int rxmem)
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{
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Error *errp = NULL;
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qdev_set_nic_properties(dev, nd);
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qdev_prop_set_uint32(dev, "rxmem", rxmem);
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qdev_prop_set_uint32(dev, "txmem", txmem);
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object_property_set_link(OBJECT(dev), OBJECT(ds),
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"axistream-connected", &errp);
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object_property_set_link(OBJECT(dev), OBJECT(cs),
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"axistream-control-connected", &errp);
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assert_no_error(errp);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
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}
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static inline void
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xilinx_axidma_init(DeviceState *dev, StreamSlave *ds, StreamSlave *cs,
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hwaddr base, qemu_irq irq, qemu_irq irq2, int freqhz)
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{
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Error *errp = NULL;
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qdev_prop_set_uint32(dev, "freqhz", freqhz);
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object_property_set_link(OBJECT(dev), OBJECT(ds),
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"axistream-connected", &errp);
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object_property_set_link(OBJECT(dev), OBJECT(cs),
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"axistream-control-connected", &errp);
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assert_no_error(errp);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, irq2);
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}
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#endif
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