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d8bdf97972
Previously this device created N subdevices which each owned an i2c bus. Now this device simply owns the N i2c busses directly. Tested: Verified devices behind mux are still accessible via qmp and i2c from within an arm32 SoC. Reviewed-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Patrick Venture <venture@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220202164533.1283668-1-venture@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
240 lines
6.1 KiB
C
240 lines
6.1 KiB
C
/*
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* I2C multiplexer for PCA954x series of I2C multiplexer/switch chips.
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*
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* Copyright 2021 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/i2c/i2c.h"
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#include "hw/i2c/i2c_mux_pca954x.h"
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#include "hw/i2c/smbus_slave.h"
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#include "hw/qdev-core.h"
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#include "hw/sysbus.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/queue.h"
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#include "qom/object.h"
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#include "trace.h"
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#define PCA9548_CHANNEL_COUNT 8
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#define PCA9546_CHANNEL_COUNT 4
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/*
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* struct Pca954xState - The pca954x state object.
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* @control: The value written to the mux control.
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* @channel: The set of i2c channel buses that act as channels which own the
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* i2c children.
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*/
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typedef struct Pca954xState {
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SMBusDevice parent;
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uint8_t control;
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bool enabled[PCA9548_CHANNEL_COUNT];
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I2CBus *bus[PCA9548_CHANNEL_COUNT];
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} Pca954xState;
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/*
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* struct Pca954xClass - The pca954x class object.
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* @nchans: The number of i2c channels this device has.
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*/
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typedef struct Pca954xClass {
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SMBusDeviceClass parent;
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uint8_t nchans;
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} Pca954xClass;
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#define TYPE_PCA954X "pca954x"
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OBJECT_DECLARE_TYPE(Pca954xState, Pca954xClass, PCA954X)
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/*
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* For each channel, if it's enabled, recursively call match on those children.
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*/
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static bool pca954x_match(I2CSlave *candidate, uint8_t address,
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bool broadcast,
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I2CNodeList *current_devs)
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{
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Pca954xState *mux = PCA954X(candidate);
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Pca954xClass *mc = PCA954X_GET_CLASS(mux);
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int i;
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/* They are talking to the mux itself (or all devices enabled). */
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if ((candidate->address == address) || broadcast) {
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I2CNode *node = g_malloc(sizeof(struct I2CNode));
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node->elt = candidate;
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QLIST_INSERT_HEAD(current_devs, node, next);
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if (!broadcast) {
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return true;
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}
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}
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for (i = 0; i < mc->nchans; i++) {
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if (!mux->enabled[i]) {
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continue;
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}
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if (i2c_scan_bus(mux->bus[i], address, broadcast,
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current_devs)) {
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if (!broadcast) {
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return true;
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}
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}
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}
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/* If we arrived here we didn't find a match, return broadcast. */
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return broadcast;
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}
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static void pca954x_enable_channel(Pca954xState *s, uint8_t enable_mask)
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{
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Pca954xClass *mc = PCA954X_GET_CLASS(s);
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int i;
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/*
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* For each channel, check if their bit is set in enable_mask and if yes,
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* enable it, otherwise disable, hide it.
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*/
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for (i = 0; i < mc->nchans; i++) {
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if (enable_mask & (1 << i)) {
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s->enabled[i] = true;
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} else {
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s->enabled[i] = false;
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}
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}
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}
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static void pca954x_write(Pca954xState *s, uint8_t data)
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{
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s->control = data;
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pca954x_enable_channel(s, data);
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trace_pca954x_write_bytes(data);
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}
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static int pca954x_write_data(SMBusDevice *d, uint8_t *buf, uint8_t len)
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{
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Pca954xState *s = PCA954X(d);
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if (len == 0) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: writing empty data\n", __func__);
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return -1;
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}
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/*
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* len should be 1, because they write one byte to enable/disable channels.
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*/
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if (len > 1) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: extra data after channel selection mask\n",
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__func__);
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return -1;
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}
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pca954x_write(s, buf[0]);
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return 0;
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}
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static uint8_t pca954x_read_byte(SMBusDevice *d)
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{
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Pca954xState *s = PCA954X(d);
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uint8_t data = s->control;
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trace_pca954x_read_data(data);
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return data;
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}
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static void pca954x_enter_reset(Object *obj, ResetType type)
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{
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Pca954xState *s = PCA954X(obj);
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/* Reset will disable all channels. */
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pca954x_write(s, 0);
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}
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I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel)
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{
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Pca954xClass *pc = PCA954X_GET_CLASS(mux);
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Pca954xState *pca954x = PCA954X(mux);
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g_assert(channel < pc->nchans);
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return pca954x->bus[channel];
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}
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static void pca9546_class_init(ObjectClass *klass, void *data)
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{
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Pca954xClass *s = PCA954X_CLASS(klass);
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s->nchans = PCA9546_CHANNEL_COUNT;
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}
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static void pca9548_class_init(ObjectClass *klass, void *data)
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{
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Pca954xClass *s = PCA954X_CLASS(klass);
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s->nchans = PCA9548_CHANNEL_COUNT;
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}
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static void pca954x_init(Object *obj)
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{
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Pca954xState *s = PCA954X(obj);
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Pca954xClass *c = PCA954X_GET_CLASS(obj);
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int i;
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/* SMBus modules. Cannot fail. */
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for (i = 0; i < c->nchans; i++) {
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g_autofree gchar *bus_name = g_strdup_printf("i2c.%d", i);
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/* start all channels as disabled. */
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s->enabled[i] = false;
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s->bus[i] = i2c_init_bus(DEVICE(s), bus_name);
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}
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}
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static void pca954x_class_init(ObjectClass *klass, void *data)
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{
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I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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SMBusDeviceClass *k = SMBUS_DEVICE_CLASS(klass);
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sc->match_and_add = pca954x_match;
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rc->phases.enter = pca954x_enter_reset;
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dc->desc = "Pca954x i2c-mux";
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k->write_data = pca954x_write_data;
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k->receive_byte = pca954x_read_byte;
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}
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static const TypeInfo pca954x_info[] = {
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{
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.name = TYPE_PCA954X,
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.parent = TYPE_SMBUS_DEVICE,
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.instance_size = sizeof(Pca954xState),
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.instance_init = pca954x_init,
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.class_size = sizeof(Pca954xClass),
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.class_init = pca954x_class_init,
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.abstract = true,
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},
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{
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.name = TYPE_PCA9546,
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.parent = TYPE_PCA954X,
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.class_init = pca9546_class_init,
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},
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{
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.name = TYPE_PCA9548,
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.parent = TYPE_PCA954X,
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.class_init = pca9548_class_init,
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},
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};
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DEFINE_TYPES(pca954x_info)
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