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ARM: NEON VP3 IDCT
15% faster VP3/Theora, 10% faster VP6 Originally committed as revision 19345 to svn://svn.ffmpeg.org/ffmpeg/trunk
This commit is contained in:
David Conrad
parent
82c9182fe3
commit
2483298ae2
@ -43,6 +43,10 @@ void ff_simple_idct_neon(DCTELEM *data);
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void ff_simple_idct_put_neon(uint8_t *dest, int line_size, DCTELEM *data);
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void ff_simple_idct_add_neon(uint8_t *dest, int line_size, DCTELEM *data);
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void ff_vp3_idct_neon(DCTELEM *data);
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void ff_vp3_idct_put_neon(uint8_t *dest, int line_size, DCTELEM *data);
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void ff_vp3_idct_add_neon(uint8_t *dest, int line_size, DCTELEM *data);
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/* XXX: local hack */
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static void (*ff_put_pixels_clamped)(const DCTELEM *block, uint8_t *pixels, int line_size);
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static void (*ff_add_pixels_clamped)(const DCTELEM *block, uint8_t *pixels, int line_size);
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@ -180,6 +184,12 @@ void dsputil_init_arm(DSPContext* c, AVCodecContext *avctx)
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c->idct_add= ff_simple_idct_add_neon;
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c->idct = ff_simple_idct_neon;
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c->idct_permutation_type = FF_PARTTRANS_IDCT_PERM;
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} else if ((CONFIG_VP3_DECODER || CONFIG_VP5_DECODER || CONFIG_VP6_DECODER || CONFIG_THEORA_DECODER) &&
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idct_algo==FF_IDCT_VP3){
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c->idct_put= ff_vp3_idct_put_neon;
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c->idct_add= ff_vp3_idct_add_neon;
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c->idct = ff_vp3_idct_neon;
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c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
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#endif
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}
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}
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@ -20,6 +20,22 @@
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#include "asm.S"
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.section .rodata
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.align 4
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vp3_idct_constants:
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.short 64277, 60547, 54491, 46341, 36410, 25080, 12785
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#define xC1S7 d0[0]
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#define xC2S6 d0[1]
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#define xC3S5 d0[2]
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#define xC4S4 d0[3]
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#define xC5S3 d1[0]
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#define xC6S2 d1[1]
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#define xC7S1 d1[2]
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.text
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.macro vp3_loop_filter
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vsubl.u8 q3, d18, d17
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vsubl.u8 q2, d16, d19
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@ -92,3 +108,269 @@ function ff_vp3_h_loop_filter_neon, export=1
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vst1.16 {d1[3]}, [ip], r1
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bx lr
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.endfunc
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function vp3_idct_start_neon
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vpush {d8-d15}
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movrel r3, vp3_idct_constants
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vld1.64 {d0-d1}, [r3,:128]
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vld1.64 {d16-d19}, [r2,:128]!
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vld1.64 {d20-d23}, [r2,:128]!
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vld1.64 {d24-d27}, [r2,:128]!
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vadd.s16 q1, q8, q12
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vsub.s16 q8, q8, q12
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vld1.64 {d28-d31}, [r2,:128]!
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.endfunc
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function vp3_idct_core_neon
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vmull.s16 q2, d18, xC1S7 // (ip[1] * C1) << 16
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vmull.s16 q3, d19, xC1S7
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vmull.s16 q4, d2, xC4S4 // ((ip[0] + ip[4]) * C4) << 16
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vmull.s16 q5, d3, xC4S4
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vmull.s16 q6, d16, xC4S4 // ((ip[0] - ip[4]) * C4) << 16
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vmull.s16 q7, d17, xC4S4
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vshrn.s32 d4, q2, #16
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vshrn.s32 d5, q3, #16
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vshrn.s32 d6, q4, #16
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vshrn.s32 d7, q5, #16
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vshrn.s32 d8, q6, #16
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vshrn.s32 d9, q7, #16
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vadd.s16 q12, q1, q3 // E = (ip[0] + ip[4]) * C4
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vadd.s16 q8, q8, q4 // F = (ip[0] - ip[4]) * C4
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vadd.s16 q1, q2, q9 // ip[1] * C1
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vmull.s16 q2, d30, xC1S7 // (ip[7] * C1) << 16
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vmull.s16 q3, d31, xC1S7
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vmull.s16 q4, d30, xC7S1 // (ip[7] * C7) << 16
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vmull.s16 q5, d31, xC7S1
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vmull.s16 q6, d18, xC7S1 // (ip[1] * C7) << 16
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vmull.s16 q7, d19, xC7S1
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vshrn.s32 d4, q2, #16
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vshrn.s32 d5, q3, #16
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vshrn.s32 d6, q4, #16 // ip[7] * C7
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vshrn.s32 d7, q5, #16
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vshrn.s32 d8, q6, #16 // ip[1] * C7
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vshrn.s32 d9, q7, #16
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vadd.s16 q2, q2, q15 // ip[7] * C1
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vadd.s16 q9, q1, q3 // A = ip[1] * C1 + ip[7] * C7
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vsub.s16 q15, q4, q2 // B = ip[1] * C7 - ip[7] * C1
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vmull.s16 q2, d22, xC5S3 // (ip[3] * C5) << 16
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vmull.s16 q3, d23, xC5S3
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vmull.s16 q4, d22, xC3S5 // (ip[3] * C3) << 16
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vmull.s16 q5, d23, xC3S5
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vmull.s16 q6, d26, xC5S3 // (ip[5] * C5) << 16
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vmull.s16 q7, d27, xC5S3
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vshrn.s32 d4, q2, #16
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vshrn.s32 d5, q3, #16
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vshrn.s32 d6, q4, #16
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vshrn.s32 d7, q5, #16
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vshrn.s32 d8, q6, #16
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vshrn.s32 d9, q7, #16
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vadd.s16 q3, q3, q11 // ip[3] * C3
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vadd.s16 q4, q4, q13 // ip[5] * C5
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vadd.s16 q1, q2, q11 // ip[3] * C5
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vadd.s16 q11, q3, q4 // C = ip[3] * C3 + ip[5] * C5
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vmull.s16 q2, d26, xC3S5 // (ip[5] * C3) << 16
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vmull.s16 q3, d27, xC3S5
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vmull.s16 q4, d20, xC2S6 // (ip[2] * C2) << 16
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vmull.s16 q5, d21, xC2S6
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vmull.s16 q6, d28, xC6S2 // (ip[6] * C6) << 16
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vmull.s16 q7, d29, xC6S2
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vshrn.s32 d4, q2, #16
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vshrn.s32 d5, q3, #16
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vshrn.s32 d6, q4, #16
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vshrn.s32 d7, q5, #16
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vshrn.s32 d8, q6, #16 // ip[6] * C6
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vshrn.s32 d9, q7, #16
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vadd.s16 q2, q2, q13 // ip[5] * C3
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vadd.s16 q3, q3, q10 // ip[2] * C2
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vsub.s16 q13, q2, q1 // D = ip[5] * C3 - ip[3] * C5
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vsub.s16 q1, q9, q11 // (A - C)
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vadd.s16 q11, q9, q11 // Cd = A + C
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vsub.s16 q9, q15, q13 // (B - D)
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vadd.s16 q13, q15, q13 // Dd = B + D
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vadd.s16 q15, q3, q4 // G = ip[2] * C2 + ip[6] * C6
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vmull.s16 q2, d2, xC4S4 // ((A - C) * C4) << 16
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vmull.s16 q3, d3, xC4S4
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vmull.s16 q4, d28, xC2S6 // (ip[6] * C2) << 16
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vmull.s16 q5, d29, xC2S6
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vmull.s16 q6, d20, xC6S2 // (ip[2] * C6) << 16
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vmull.s16 q7, d21, xC6S2
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vshrn.s32 d4, q2, #16
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vshrn.s32 d5, q3, #16
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vshrn.s32 d6, q4, #16
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vshrn.s32 d7, q5, #16
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vshrn.s32 d8, q6, #16 // ip[2] * C6
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vmull.s16 q5, d18, xC4S4 // ((B - D) * C4) << 16
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vmull.s16 q6, d19, xC4S4
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vshrn.s32 d9, q7, #16
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vadd.s16 q3, q3, q14 // ip[6] * C2
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vadd.s16 q10, q1, q2 // Ad = (A - C) * C4
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vsub.s16 q14, q4, q3 // H = ip[2] * C6 - ip[6] * C2
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bx lr
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.endfunc
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.macro VP3_IDCT_END type
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function vp3_idct_end_\type\()_neon
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.ifc \type, col
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vdup.16 q0, r3
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vadd.s16 q12, q12, q0
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vadd.s16 q8, q8, q0
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.endif
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vshrn.s32 d2, q5, #16
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vshrn.s32 d3, q6, #16
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vadd.s16 q2, q12, q15 // Gd = E + G
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vadd.s16 q9, q1, q9 // (B - D) * C4
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vsub.s16 q12, q12, q15 // Ed = E - G
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vsub.s16 q3, q8, q10 // Fd = F - Ad
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vadd.s16 q10, q8, q10 // Add = F + Ad
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vadd.s16 q4, q9, q14 // Hd = Bd + H
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vsub.s16 q14, q9, q14 // Bdd = Bd - H
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vadd.s16 q8, q2, q11 // [0] = Gd + Cd
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vsub.s16 q15, q2, q11 // [7] = Gd - Cd
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vadd.s16 q9, q10, q4 // [1] = Add + Hd
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vsub.s16 q10, q10, q4 // [2] = Add - Hd
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vadd.s16 q11, q12, q13 // [3] = Ed + Dd
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vsub.s16 q12, q12, q13 // [4] = Ed - Dd
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.ifc \type, row
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vtrn.16 q8, q9
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.endif
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vadd.s16 q13, q3, q14 // [5] = Fd + Bdd
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vsub.s16 q14, q3, q14 // [6] = Fd - Bdd
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.ifc \type, row
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// 8x8 transpose
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vtrn.16 q10, q11
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vtrn.16 q12, q13
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vtrn.16 q14, q15
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vtrn.32 q8, q10
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vtrn.32 q9, q11
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vtrn.32 q12, q14
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vtrn.32 q13, q15
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vswp d17, d24
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vswp d19, d26
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vadd.s16 q1, q8, q12
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vswp d21, d28
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vsub.s16 q8, q8, q12
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vswp d23, d30
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.endif
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bx lr
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.endfunc
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.endm
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VP3_IDCT_END row
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VP3_IDCT_END col
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function ff_vp3_idct_neon, export=1
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mov ip, lr
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mov r2, r0
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bl vp3_idct_start_neon
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bl vp3_idct_end_row_neon
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mov r3, #8
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bl vp3_idct_core_neon
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bl vp3_idct_end_col_neon
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mov lr, ip
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vpop {d8-d15}
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vshr.s16 q8, q8, #4
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vshr.s16 q9, q9, #4
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vshr.s16 q10, q10, #4
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vshr.s16 q11, q11, #4
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vshr.s16 q12, q12, #4
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vst1.64 {d16-d19}, [r0,:128]!
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vshr.s16 q13, q13, #4
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vshr.s16 q14, q14, #4
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vst1.64 {d20-d23}, [r0,:128]!
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vshr.s16 q15, q15, #4
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vst1.64 {d24-d27}, [r0,:128]!
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vst1.64 {d28-d31}, [r0,:128]!
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bx lr
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.endfunc
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function ff_vp3_idct_put_neon, export=1
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mov ip, lr
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bl vp3_idct_start_neon
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bl vp3_idct_end_row_neon
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mov r3, #8
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add r3, r3, #2048 // convert signed pixel to unsigned
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bl vp3_idct_core_neon
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bl vp3_idct_end_col_neon
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mov lr, ip
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vpop {d8-d15}
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vqshrun.s16 d0, q8, #4
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vqshrun.s16 d1, q9, #4
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vqshrun.s16 d2, q10, #4
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vqshrun.s16 d3, q11, #4
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vst1.64 {d0}, [r0,:64], r1
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vqshrun.s16 d4, q12, #4
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vst1.64 {d1}, [r0,:64], r1
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vqshrun.s16 d5, q13, #4
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vst1.64 {d2}, [r0,:64], r1
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vqshrun.s16 d6, q14, #4
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vst1.64 {d3}, [r0,:64], r1
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vqshrun.s16 d7, q15, #4
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vst1.64 {d4}, [r0,:64], r1
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vst1.64 {d5}, [r0,:64], r1
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vst1.64 {d6}, [r0,:64], r1
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vst1.64 {d7}, [r0,:64], r1
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bx lr
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.endfunc
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function ff_vp3_idct_add_neon, export=1
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mov ip, lr
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bl vp3_idct_start_neon
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bl vp3_idct_end_row_neon
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mov r3, #8
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bl vp3_idct_core_neon
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bl vp3_idct_end_col_neon
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mov lr, ip
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vpop {d8-d15}
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mov r2, r0
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vld1.64 {d0}, [r0,:64], r1
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vshr.s16 q8, q8, #4
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vld1.64 {d1}, [r0,:64], r1
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vshr.s16 q9, q9, #4
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vld1.64 {d2}, [r0,:64], r1
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vaddw.u8 q8, q8, d0
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vld1.64 {d3}, [r0,:64], r1
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vaddw.u8 q9, q9, d1
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vld1.64 {d4}, [r0,:64], r1
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vshr.s16 q10, q10, #4
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vld1.64 {d5}, [r0,:64], r1
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vshr.s16 q11, q11, #4
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vld1.64 {d6}, [r0,:64], r1
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vqmovun.s16 d0, q8
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vld1.64 {d7}, [r0,:64], r1
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vqmovun.s16 d1, q9
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vaddw.u8 q10, q10, d2
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vaddw.u8 q11, q11, d3
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vshr.s16 q12, q12, #4
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vshr.s16 q13, q13, #4
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vqmovun.s16 d2, q10
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vqmovun.s16 d3, q11
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vaddw.u8 q12, q12, d4
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vaddw.u8 q13, q13, d5
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vshr.s16 q14, q14, #4
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vshr.s16 q15, q15, #4
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vst1.64 {d0}, [r2,:64], r1
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vqmovun.s16 d4, q12
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vst1.64 {d1}, [r2,:64], r1
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vqmovun.s16 d5, q13
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vst1.64 {d2}, [r2,:64], r1
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vaddw.u8 q14, q14, d6
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vst1.64 {d3}, [r2,:64], r1
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vaddw.u8 q15, q15, d7
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vst1.64 {d4}, [r2,:64], r1
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vqmovun.s16 d6, q14
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vst1.64 {d5}, [r2,:64], r1
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vqmovun.s16 d7, q15
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vst1.64 {d6}, [r2,:64], r1
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vst1.64 {d7}, [r2,:64], r1
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bx lr
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.endfunc
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