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x86: Use consistent 3dnowext function and macro name suffixes
Currently there is a wild mix of 3dn2/3dnow2/3dnowext. Switching to "3dnowext", which is a more common name of the CPU flag, as reported e.g. by the Linux kernel, unifies this.
This commit is contained in:
Diego Biurrun
parent
d3e0766fc0
commit
ca844b7be9
@ -2358,9 +2358,9 @@ static void ac3_downmix_sse(float (*samples)[256], float (*matrix)[2],
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}
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#if HAVE_6REGS
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static void vector_fmul_window_3dnow2(float *dst, const float *src0,
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const float *src1, const float *win,
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int len)
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static void vector_fmul_window_3dnowext(float *dst, const float *src0,
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const float *src1, const float *win,
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int len)
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{
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x86_reg i = -len * 4;
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x86_reg j = len * 4 - 8;
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@ -2809,11 +2809,11 @@ static void dsputil_init_3dnow(DSPContext *c, AVCodecContext *avctx,
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#endif
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}
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static void dsputil_init_3dnow2(DSPContext *c, AVCodecContext *avctx,
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int mm_flags)
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static void dsputil_init_3dnowext(DSPContext *c, AVCodecContext *avctx,
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int mm_flags)
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{
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#if HAVE_6REGS && HAVE_INLINE_ASM
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c->vector_fmul_window = vector_fmul_window_3dnow2;
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c->vector_fmul_window = vector_fmul_window_3dnowext;
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#endif
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}
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@ -3051,7 +3051,7 @@ void ff_dsputil_init_mmx(DSPContext *c, AVCodecContext *avctx)
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dsputil_init_3dnow(c, avctx, mm_flags);
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if (mm_flags & AV_CPU_FLAG_3DNOWEXT && HAVE_AMD3DNOWEXT)
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dsputil_init_3dnow2(c, avctx, mm_flags);
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dsputil_init_3dnowext(c, avctx, mm_flags);
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if (mm_flags & AV_CPU_FLAG_SSE && HAVE_SSE)
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dsputil_init_sse(c, avctx, mm_flags);
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@ -34,9 +34,9 @@ av_cold void ff_fft_init_mmx(FFTContext *s)
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}
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if (has_vectors & AV_CPU_FLAG_3DNOWEXT && HAVE_AMD3DNOWEXT) {
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/* 3DNowEx for K7 */
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s->imdct_calc = ff_imdct_calc_3dnow2;
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s->imdct_half = ff_imdct_half_3dnow2;
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s->fft_calc = ff_fft_calc_3dnow2;
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s->imdct_calc = ff_imdct_calc_3dnowext;
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s->imdct_half = ff_imdct_half_3dnowext;
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s->fft_calc = ff_fft_calc_3dnowext;
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}
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#endif
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if (has_vectors & AV_CPU_FLAG_SSE && HAVE_SSE) {
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@ -25,12 +25,12 @@ void ff_fft_permute_sse(FFTContext *s, FFTComplex *z);
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void ff_fft_calc_avx(FFTContext *s, FFTComplex *z);
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void ff_fft_calc_sse(FFTContext *s, FFTComplex *z);
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void ff_fft_calc_3dnow(FFTContext *s, FFTComplex *z);
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void ff_fft_calc_3dnow2(FFTContext *s, FFTComplex *z);
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void ff_fft_calc_3dnowext(FFTContext *s, FFTComplex *z);
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void ff_imdct_calc_3dnow(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_3dnow(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_calc_3dnow2(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_3dnow2(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_calc_3dnowext(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_3dnowext(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_calc_sse(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_sse(FFTContext *s, FFTSample *output, const FFTSample *input);
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void ff_imdct_half_avx(FFTContext *s, FFTSample *output, const FFTSample *input);
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@ -93,14 +93,14 @@ cextern cos_ %+ i
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SECTION_TEXT
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%macro T2_3DN 4 ; z0, z1, mem0, mem1
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%macro T2_3DNOW 4 ; z0, z1, mem0, mem1
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mova %1, %3
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mova %2, %1
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pfadd %1, %4
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pfsub %2, %4
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%endmacro
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%macro T4_3DN 6 ; z0, z1, z2, z3, tmp0, tmp1
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%macro T4_3DNOW 6 ; z0, z1, z2, z3, tmp0, tmp1
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mova %5, %3
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pfsub %3, %4
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pfadd %5, %4 ; {t6,t5}
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@ -444,13 +444,13 @@ fft16_sse:
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ret
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%macro FFT48_3DN 0
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%macro FFT48_3DNOW 0
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align 16
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fft4 %+ SUFFIX:
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T2_3DN m0, m1, Z(0), Z(1)
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T2_3DNOW m0, m1, Z(0), Z(1)
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mova m2, Z(2)
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mova m3, Z(3)
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T4_3DN m0, m1, m2, m3, m4, m5
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T4_3DNOW m0, m1, m2, m3, m4, m5
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PUNPCK m0, m1, m4
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PUNPCK m2, m3, m5
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mova Z(0), m0
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@ -461,14 +461,14 @@ fft4 %+ SUFFIX:
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align 16
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fft8 %+ SUFFIX:
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T2_3DN m0, m1, Z(0), Z(1)
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T2_3DNOW m0, m1, Z(0), Z(1)
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mova m2, Z(2)
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mova m3, Z(3)
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T4_3DN m0, m1, m2, m3, m4, m5
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T4_3DNOW m0, m1, m2, m3, m4, m5
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mova Z(0), m0
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mova Z(2), m2
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T2_3DN m4, m5, Z(4), Z(5)
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T2_3DN m6, m7, Z2(6), Z2(7)
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T2_3DNOW m4, m5, Z(4), Z(5)
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T2_3DNOW m6, m7, Z2(6), Z2(7)
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PSWAPD m0, m5
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PSWAPD m2, m7
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pxor m0, [ps_m1p1]
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@ -477,12 +477,12 @@ fft8 %+ SUFFIX:
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pfadd m7, m2
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pfmul m5, [ps_root2]
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pfmul m7, [ps_root2]
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T4_3DN m1, m3, m5, m7, m0, m2
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T4_3DNOW m1, m3, m5, m7, m0, m2
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mova Z(5), m5
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mova Z2(7), m7
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mova m0, Z(0)
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mova m2, Z(2)
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T4_3DN m0, m2, m4, m6, m5, m7
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T4_3DNOW m0, m2, m4, m6, m5, m7
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PUNPCK m0, m1, m5
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PUNPCK m2, m3, m7
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mova Z(0), m0
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@ -500,7 +500,7 @@ fft8 %+ SUFFIX:
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%if ARCH_X86_32
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%macro PSWAPD 2
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%if cpuflag(3dnow2)
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%if cpuflag(3dnowext)
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pswapd %1, %2
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%elifidn %1, %2
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movd [r0+12], %1
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@ -512,11 +512,11 @@ fft8 %+ SUFFIX:
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%endif
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%endmacro
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INIT_MMX 3dnow2
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FFT48_3DN
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INIT_MMX 3dnowext
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FFT48_3DNOW
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INIT_MMX 3dnow
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FFT48_3DN
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FFT48_3DNOW
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%endif
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%define Z(x) [zcq + o1q*(x&6) + mmsize*(x&1)]
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@ -633,7 +633,7 @@ cglobal fft_calc, 2,5,8
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%if ARCH_X86_32
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INIT_MMX 3dnow
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FFT_CALC_FUNC
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INIT_MMX 3dnow2
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INIT_MMX 3dnowext
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FFT_CALC_FUNC
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%endif
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INIT_XMM sse
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@ -727,7 +727,7 @@ cglobal imdct_calc, 3,5,3
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%if ARCH_X86_32
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INIT_MMX 3dnow
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IMDCT_CALC_FUNC
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INIT_MMX 3dnow2
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INIT_MMX 3dnowext
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IMDCT_CALC_FUNC
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%endif
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@ -743,8 +743,8 @@ INIT_MMX 3dnow
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%define unpckhps punpckhdq
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DECL_PASS pass_3dnow, PASS_SMALL 1, [wq], [wq+o1q]
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DECL_PASS pass_interleave_3dnow, PASS_BIG 0
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%define pass_3dnow2 pass_3dnow
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%define pass_interleave_3dnow2 pass_interleave_3dnow
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%define pass_3dnowext pass_3dnow
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%define pass_interleave_3dnowext pass_interleave_3dnow
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%endif
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%ifdef PIC
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@ -813,7 +813,7 @@ DECL_FFT 5, _interleave
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INIT_MMX 3dnow
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DECL_FFT 4
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DECL_FFT 4, _interleave
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INIT_MMX 3dnow2
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INIT_MMX 3dnowext
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DECL_FFT 4
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DECL_FFT 4, _interleave
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%endif
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@ -845,7 +845,7 @@ INIT_XMM sse
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PSWAPD m5, m3
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pfmul m2, m3
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pfmul m6, m5
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%if cpuflag(3dnow2)
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%if cpuflag(3dnowext)
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pfpnacc m0, m4
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pfpnacc m2, m6
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%else
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@ -1018,7 +1018,7 @@ cglobal imdct_half, 3,12,8; FFTContext *s, FFTSample *output, const FFTSample *i
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xor r4, r4
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sub r4, r3
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%endif
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%if notcpuflag(3dnow2) && mmsize == 8
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%if notcpuflag(3dnowext) && mmsize == 8
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movd m7, [ps_m1m1m1m1]
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%endif
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.pre:
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@ -1102,7 +1102,7 @@ DECL_IMDCT POSROTATESHUF
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INIT_MMX 3dnow
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DECL_IMDCT POSROTATESHUF_3DNOW
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INIT_MMX 3dnow2
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INIT_MMX 3dnowext
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DECL_IMDCT POSROTATESHUF_3DNOW
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%endif
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@ -249,7 +249,7 @@ FLOAT_TO_INT16_INTERLEAVE2 sse2
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%macro PSWAPD_SSE 2
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pshufw %1, %2, 0x4e
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%endmacro
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%macro PSWAPD_3DN1 2
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%macro PSWAPD_3DNOW 2
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movq %1, %2
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psrlq %1, 32
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punpckldq %1, %2
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@ -306,10 +306,10 @@ cglobal float_to_int16_interleave6_%1, 2,8,0, dst, src, src1, src2, src3, src4,
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%define pswapd PSWAPD_SSE
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FLOAT_TO_INT16_INTERLEAVE6 sse
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%define cvtps2pi pf2id
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%define pswapd PSWAPD_3DN1
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%define pswapd PSWAPD_3DNOW
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FLOAT_TO_INT16_INTERLEAVE6 3dnow
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%undef pswapd
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FLOAT_TO_INT16_INTERLEAVE6 3dn2
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FLOAT_TO_INT16_INTERLEAVE6 3dnowext
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%undef cvtps2pi
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;-----------------------------------------------------------------------------
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@ -46,7 +46,7 @@ void ff_float_to_int16_interleave2_sse2 (int16_t *dst, const float **src, long l
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void ff_float_to_int16_interleave6_sse(int16_t *dst, const float **src, int len);
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void ff_float_to_int16_interleave6_3dnow(int16_t *dst, const float **src, int len);
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void ff_float_to_int16_interleave6_3dn2(int16_t *dst, const float **src, int len);
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void ff_float_to_int16_interleave6_3dnowext(int16_t *dst, const float **src, int len);
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#define ff_float_to_int16_interleave6_sse2 ff_float_to_int16_interleave6_sse
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@ -74,9 +74,11 @@ FLOAT_TO_INT16_INTERLEAVE(3dnow)
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FLOAT_TO_INT16_INTERLEAVE(sse)
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FLOAT_TO_INT16_INTERLEAVE(sse2)
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static void float_to_int16_interleave_3dn2(int16_t *dst, const float **src, long len, int channels){
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static void float_to_int16_interleave_3dnowext(int16_t *dst, const float **src,
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long len, int channels)
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{
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if(channels==6)
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ff_float_to_int16_interleave6_3dn2(dst, src, len);
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ff_float_to_int16_interleave6_3dnowext(dst, src, len);
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else
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float_to_int16_interleave_3dnow(dst, src, len, channels);
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}
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@ -126,7 +128,7 @@ void ff_fmt_convert_init_x86(FmtConvertContext *c, AVCodecContext *avctx)
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}
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if (HAVE_AMD3DNOWEXT && mm_flags & AV_CPU_FLAG_3DNOWEXT) {
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if(!(avctx->flags & CODEC_FLAG_BITEXACT)){
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c->float_to_int16_interleave = float_to_int16_interleave_3dn2;
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c->float_to_int16_interleave = float_to_int16_interleave_3dnowext;
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}
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}
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if (HAVE_SSE && mm_flags & AV_CPU_FLAG_SSE) {
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@ -557,7 +557,7 @@ SECTION .note.GNU-stack noalloc noexec nowrite progbits
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%assign cpuflags_mmx (1<<0)
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%assign cpuflags_mmx2 (1<<1) | cpuflags_mmx
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%assign cpuflags_3dnow (1<<2) | cpuflags_mmx
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%assign cpuflags_3dnow2 (1<<3) | cpuflags_3dnow
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%assign cpuflags_3dnowext (1<<3) | cpuflags_3dnow
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%assign cpuflags_sse (1<<4) | cpuflags_mmx2
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%assign cpuflags_sse2 (1<<5) | cpuflags_sse
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%assign cpuflags_sse2slow (1<<6) | cpuflags_sse2
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