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Merge commit '930e26a3ea9d223e04bac4cdde13697cec770031'
* commit '930e26a3ea9d223e04bac4cdde13697cec770031': x86: h264qpel: Only define mmxext QPEL functions if H264QPEL is enabled x86: PABSW: port to cpuflags x86: vc1dsp: port to cpuflags rtmp: Use av_strlcat instead of strncat Conflicts: libavcodec/x86/h264_qpel.c Merged-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
Michael Niedermayer
commit
e859339e7a
@ -1286,6 +1286,6 @@ QPEL16_OP(mc31, MMX)\
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QPEL16_OP(mc32, MMX)\
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QPEL16_OP(mc33, MMX)
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#if CONFIG_H264QPEL && ARCH_X86_32 && HAVE_YASM // ARCH_X86_64 implies sse2+
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#if ARCH_X86_32 && HAVE_YASM && CONFIG_H264QPEL // ARCH_X86_64 implies SSE2+
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QPEL16(mmxext)
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#endif
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@ -34,7 +34,13 @@ section .text
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punpckl%1 m%2, m%4
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%endmacro
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%macro STORE_4_WORDS_MMX 6
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%macro STORE_4_WORDS 6
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%if cpuflag(sse4)
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pextrw %1, %5, %6+0
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pextrw %2, %5, %6+1
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pextrw %3, %5, %6+2
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pextrw %4, %5, %6+3
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%else
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movd %6d, %5
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%if mmsize==16
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psrldq %5, 4
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@ -48,13 +54,7 @@ section .text
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mov %3, %6w
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shr %6, 16
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mov %4, %6w
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%endmacro
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%macro STORE_4_WORDS_SSE4 6
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pextrw %1, %5, %6+0
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pextrw %2, %5, %6+1
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pextrw %3, %5, %6+2
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pextrw %4, %5, %6+3
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%endif
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%endmacro
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; in: p1 p0 q0 q1, clobbers p0
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@ -200,14 +200,14 @@ section .text
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VC1_FILTER %1
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punpcklbw m0, m1
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%if %0 > 1
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STORE_4_WORDS_MMX [r0-1], [r0+r1-1], [r0+2*r1-1], [r0+r3-1], m0, %2
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STORE_4_WORDS [r0-1], [r0+r1-1], [r0+2*r1-1], [r0+r3-1], m0, %2
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%if %1 > 4
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psrldq m0, 4
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STORE_4_WORDS_MMX [r4-1], [r4+r1-1], [r4+2*r1-1], [r4+r3-1], m0, %2
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STORE_4_WORDS [r4-1], [r4+r1-1], [r4+2*r1-1], [r4+r3-1], m0, %2
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%endif
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%else
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STORE_4_WORDS_SSE4 [r0-1], [r0+r1-1], [r0+2*r1-1], [r0+r3-1], m0, 0
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STORE_4_WORDS_SSE4 [r4-1], [r4+r1-1], [r4+2*r1-1], [r4+r3-1], m0, 4
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STORE_4_WORDS [r0-1], [r0+r1-1], [r0+2*r1-1], [r0+r3-1], m0, 0
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STORE_4_WORDS [r4-1], [r4+r1-1], [r4+2*r1-1], [r4+r3-1], m0, 4
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%endif
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%endmacro
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@ -228,92 +228,90 @@ section .text
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imul r2, 0x01010101
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%endmacro
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%macro VC1_LF_MMX 1
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INIT_MMX
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cglobal vc1_v_loop_filter_internal_%1
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%macro VC1_LF 0
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cglobal vc1_v_loop_filter_internal
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VC1_V_LOOP_FILTER 4, d
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ret
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cglobal vc1_h_loop_filter_internal_%1
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cglobal vc1_h_loop_filter_internal
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VC1_H_LOOP_FILTER 4, r4
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ret
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; void ff_vc1_v_loop_filter4_mmx2(uint8_t *src, int stride, int pq)
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cglobal vc1_v_loop_filter4_%1, 3,5,0
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; void ff_vc1_v_loop_filter4_mmxext(uint8_t *src, int stride, int pq)
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cglobal vc1_v_loop_filter4, 3,5,0
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START_V_FILTER
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call vc1_v_loop_filter_internal_%1
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call vc1_v_loop_filter_internal
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RET
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; void ff_vc1_h_loop_filter4_mmx2(uint8_t *src, int stride, int pq)
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cglobal vc1_h_loop_filter4_%1, 3,5,0
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; void ff_vc1_h_loop_filter4_mmxext(uint8_t *src, int stride, int pq)
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cglobal vc1_h_loop_filter4, 3,5,0
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START_H_FILTER 4
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call vc1_h_loop_filter_internal_%1
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call vc1_h_loop_filter_internal
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RET
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; void ff_vc1_v_loop_filter8_mmx2(uint8_t *src, int stride, int pq)
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cglobal vc1_v_loop_filter8_%1, 3,5,0
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; void ff_vc1_v_loop_filter8_mmxext(uint8_t *src, int stride, int pq)
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cglobal vc1_v_loop_filter8, 3,5,0
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START_V_FILTER
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call vc1_v_loop_filter_internal_%1
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call vc1_v_loop_filter_internal
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add r4, 4
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add r0, 4
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call vc1_v_loop_filter_internal_%1
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call vc1_v_loop_filter_internal
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RET
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; void ff_vc1_h_loop_filter8_mmx2(uint8_t *src, int stride, int pq)
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cglobal vc1_h_loop_filter8_%1, 3,5,0
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; void ff_vc1_h_loop_filter8_mmxext(uint8_t *src, int stride, int pq)
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cglobal vc1_h_loop_filter8, 3,5,0
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START_H_FILTER 4
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call vc1_h_loop_filter_internal_%1
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call vc1_h_loop_filter_internal
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lea r0, [r0+4*r1]
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call vc1_h_loop_filter_internal_%1
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call vc1_h_loop_filter_internal
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RET
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%endmacro
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%define PABSW PABSW_MMXEXT
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VC1_LF_MMX mmx2
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INIT_MMX mmxext
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VC1_LF
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INIT_XMM
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INIT_XMM sse2
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; void ff_vc1_v_loop_filter8_sse2(uint8_t *src, int stride, int pq)
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cglobal vc1_v_loop_filter8_sse2, 3,5,8
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cglobal vc1_v_loop_filter8, 3,5,8
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START_V_FILTER
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VC1_V_LOOP_FILTER 8, q
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RET
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; void ff_vc1_h_loop_filter8_sse2(uint8_t *src, int stride, int pq)
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cglobal vc1_h_loop_filter8_sse2, 3,6,8
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cglobal vc1_h_loop_filter8, 3,6,8
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START_H_FILTER 8
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VC1_H_LOOP_FILTER 8, r5
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RET
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%define PABSW PABSW_SSSE3
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INIT_MMX
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INIT_MMX ssse3
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; void ff_vc1_v_loop_filter4_ssse3(uint8_t *src, int stride, int pq)
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cglobal vc1_v_loop_filter4_ssse3, 3,5,0
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cglobal vc1_v_loop_filter4, 3,5,0
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START_V_FILTER
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VC1_V_LOOP_FILTER 4, d
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RET
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; void ff_vc1_h_loop_filter4_ssse3(uint8_t *src, int stride, int pq)
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cglobal vc1_h_loop_filter4_ssse3, 3,5,0
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cglobal vc1_h_loop_filter4, 3,5,0
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START_H_FILTER 4
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VC1_H_LOOP_FILTER 4, r4
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RET
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INIT_XMM
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INIT_XMM ssse3
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; void ff_vc1_v_loop_filter8_ssse3(uint8_t *src, int stride, int pq)
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cglobal vc1_v_loop_filter8_ssse3, 3,5,8
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cglobal vc1_v_loop_filter8, 3,5,8
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START_V_FILTER
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VC1_V_LOOP_FILTER 8, q
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RET
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; void ff_vc1_h_loop_filter8_ssse3(uint8_t *src, int stride, int pq)
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cglobal vc1_h_loop_filter8_ssse3, 3,6,8
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cglobal vc1_h_loop_filter8, 3,6,8
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START_H_FILTER 8
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VC1_H_LOOP_FILTER 8, r5
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RET
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INIT_XMM sse4
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; void ff_vc1_h_loop_filter8_sse4(uint8_t *src, int stride, int pq)
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cglobal vc1_h_loop_filter8_sse4, 3,5,8
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cglobal vc1_h_loop_filter8, 3,5,8
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START_H_FILTER 8
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VC1_H_LOOP_FILTER 8
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RET
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@ -49,7 +49,7 @@ static void vc1_h_loop_filter16_ ## EXT(uint8_t *src, int stride, int pq) \
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}
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#if HAVE_YASM
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LOOP_FILTER(mmx2)
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LOOP_FILTER(mmxext)
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LOOP_FILTER(sse2)
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LOOP_FILTER(ssse3)
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@ -98,7 +98,7 @@ av_cold void ff_vc1dsp_init_x86(VC1DSPContext *dsp)
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}
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if (mm_flags & AV_CPU_FLAG_MMXEXT) {
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ASSIGN_LF(mmx2);
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ASSIGN_LF(mmxext);
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[0] = ff_avg_vc1_chroma_mc8_nornd_mmx2;
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} else if (mm_flags & AV_CPU_FLAG_3DNOW) {
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[0] = ff_avg_vc1_chroma_mc8_nornd_3dnow;
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@ -145,13 +145,21 @@
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%endif
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%endmacro
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; PABSW macros assume %1 != %2, while ABS1/2 macros work in-place
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%macro PABSW_MMX 2
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; PABSW macro assumes %1 != %2, while ABS1/2 macros work in-place
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%macro PABSW 2
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%if cpuflag(ssse3)
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pabsw %1, %2
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%elif cpuflag(mmxext)
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pxor %1, %1
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psubw %1, %2
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pmaxsw %1, %2
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%else
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pxor %1, %1
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pcmpgtw %1, %2
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pxor %2, %1
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psubw %2, %1
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SWAP %1, %2
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%endif
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%endmacro
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%macro PSIGNW_MMX 2
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@ -159,16 +167,6 @@
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psubw %1, %2
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%endmacro
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%macro PABSW_MMXEXT 2
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pxor %1, %1
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psubw %1, %2
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pmaxsw %1, %2
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%endmacro
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%macro PABSW_SSSE3 2
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pabsw %1, %2
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%endmacro
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%macro PSIGNW_SSSE3 2
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psignw %1, %2
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%endmacro
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