mirror of
https://github.com/xenia-project/FFmpeg.git
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145 lines
3.5 KiB
NASM
145 lines
3.5 KiB
NASM
;******************************************************************************
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;* SIMD-optimized JPEG2000 DSP functions
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;* Copyright (c) 2014 Nicolas Bertrand
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;* Copyright (c) 2015 James Almer
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA 32
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pf_ict0: times 8 dd 1.402
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pf_ict1: times 8 dd 0.34413
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pf_ict2: times 8 dd 0.71414
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pf_ict3: times 8 dd 1.772
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SECTION .text
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;***********************************************************************
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; ff_ict_float_<opt>(float *src0, float *src1, float *src2, int csize)
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;***********************************************************************
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%macro ICT_FLOAT 1
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cglobal ict_float, 4, 4, %1, src0, src1, src2, csize
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shl csized, 2
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add src0q, csizeq
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add src1q, csizeq
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add src2q, csizeq
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neg csizeq
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movaps m6, [pf_ict0]
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movaps m7, [pf_ict1]
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%define ICT0 m6
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%define ICT1 m7
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%if ARCH_X86_64
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movaps m8, [pf_ict2]
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%define ICT2 m8
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%if cpuflag(avx)
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movaps m3, [pf_ict3]
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%define ICT3 m3
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%else
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movaps m9, [pf_ict3]
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%define ICT3 m9
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%endif
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%else ; ARCH_X86_32
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%define ICT2 [pf_ict2]
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%if cpuflag(avx)
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movaps m3, [pf_ict3]
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%define ICT3 m3
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%else
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%define ICT3 [pf_ict3]
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%endif
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%endif ; ARCH
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align 16
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.loop:
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movaps m0, [src0q+csizeq]
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movaps m1, [src1q+csizeq]
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movaps m2, [src2q+csizeq]
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%if cpuflag(avx)
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mulps m5, m1, ICT1
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mulps m4, m2, ICT0
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mulps m1, m1, ICT3
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mulps m2, m2, ICT2
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subps m5, m0, m5
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%else ; sse
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movaps m3, m1
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movaps m4, m2
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movaps m5, m0
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mulps m3, ICT1
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mulps m4, ICT0
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mulps m1, ICT3
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mulps m2, ICT2
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subps m5, m3
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%endif
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addps m4, m4, m0
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addps m0, m0, m1
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subps m5, m5, m2
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movaps [src0q+csizeq], m4
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movaps [src2q+csizeq], m0
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movaps [src1q+csizeq], m5
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add csizeq, mmsize
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jl .loop
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REP_RET
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%endmacro
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INIT_XMM sse
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ICT_FLOAT 10
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INIT_YMM avx
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ICT_FLOAT 9
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;***************************************************************************
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; ff_rct_int_<opt>(int32_t *src0, int32_t *src1, int32_t *src2, int csize)
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;***************************************************************************
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%macro RCT_INT 0
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cglobal rct_int, 4, 4, 4, src0, src1, src2, csize
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shl csized, 2
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add src0q, csizeq
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add src1q, csizeq
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add src2q, csizeq
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neg csizeq
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align 16
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.loop:
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mova m1, [src1q+csizeq]
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mova m2, [src2q+csizeq]
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mova m0, [src0q+csizeq]
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paddd m3, m1, m2
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psrad m3, 2
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psubd m0, m3
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paddd m1, m0
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paddd m2, m0
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mova [src1q+csizeq], m0
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mova [src2q+csizeq], m1
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mova [src0q+csizeq], m2
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add csizeq, mmsize
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jl .loop
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REP_RET
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%endmacro
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INIT_XMM sse2
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RCT_INT
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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RCT_INT
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%endif
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