mirror of
https://github.com/xenia-project/FFmpeg.git
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bf90abe1dd
* commit '5bcbb516f2ff45290ef7995b081762e668693672': arm: Add X() around all references to extern symbols Merged-by: Michael Niedermayer <michaelni@gmx.at>
393 lines
14 KiB
ArmAsm
393 lines
14 KiB
ArmAsm
/*
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* ARM NEON optimised Format Conversion Utils
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* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "config.h"
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#include "libavutil/arm/asm.S"
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function ff_float_to_int16_neon, export=1
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subs r2, r2, #8
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vld1.64 {d0-d1}, [r1,:128]!
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vcvt.s32.f32 q8, q0, #16
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vld1.64 {d2-d3}, [r1,:128]!
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vcvt.s32.f32 q9, q1, #16
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beq 3f
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bics ip, r2, #15
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beq 2f
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1: subs ip, ip, #16
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vshrn.s32 d4, q8, #16
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vld1.64 {d0-d1}, [r1,:128]!
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vcvt.s32.f32 q0, q0, #16
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vshrn.s32 d5, q9, #16
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vld1.64 {d2-d3}, [r1,:128]!
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vcvt.s32.f32 q1, q1, #16
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vshrn.s32 d6, q0, #16
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vst1.64 {d4-d5}, [r0,:128]!
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vshrn.s32 d7, q1, #16
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vld1.64 {d16-d17},[r1,:128]!
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vcvt.s32.f32 q8, q8, #16
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vld1.64 {d18-d19},[r1,:128]!
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vcvt.s32.f32 q9, q9, #16
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vst1.64 {d6-d7}, [r0,:128]!
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bne 1b
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ands r2, r2, #15
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beq 3f
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2: vld1.64 {d0-d1}, [r1,:128]!
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vshrn.s32 d4, q8, #16
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vcvt.s32.f32 q0, q0, #16
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vld1.64 {d2-d3}, [r1,:128]!
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vshrn.s32 d5, q9, #16
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vcvt.s32.f32 q1, q1, #16
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vshrn.s32 d6, q0, #16
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vst1.64 {d4-d5}, [r0,:128]!
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vshrn.s32 d7, q1, #16
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vst1.64 {d6-d7}, [r0,:128]!
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bx lr
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3: vshrn.s32 d4, q8, #16
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vshrn.s32 d5, q9, #16
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vst1.64 {d4-d5}, [r0,:128]!
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bx lr
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endfunc
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function ff_float_to_int16_interleave_neon, export=1
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cmp r3, #2
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itt lt
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ldrlt r1, [r1]
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blt X(ff_float_to_int16_neon)
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bne 4f
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ldr r3, [r1]
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ldr r1, [r1, #4]
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subs r2, r2, #8
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vld1.64 {d0-d1}, [r3,:128]!
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vcvt.s32.f32 q8, q0, #16
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vld1.64 {d2-d3}, [r3,:128]!
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vcvt.s32.f32 q9, q1, #16
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vld1.64 {d20-d21},[r1,:128]!
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vcvt.s32.f32 q10, q10, #16
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vld1.64 {d22-d23},[r1,:128]!
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vcvt.s32.f32 q11, q11, #16
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beq 3f
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bics ip, r2, #15
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beq 2f
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1: subs ip, ip, #16
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vld1.64 {d0-d1}, [r3,:128]!
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vcvt.s32.f32 q0, q0, #16
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vsri.32 q10, q8, #16
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vld1.64 {d2-d3}, [r3,:128]!
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vcvt.s32.f32 q1, q1, #16
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vld1.64 {d24-d25},[r1,:128]!
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vcvt.s32.f32 q12, q12, #16
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vld1.64 {d26-d27},[r1,:128]!
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vsri.32 q11, q9, #16
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vst1.64 {d20-d21},[r0,:128]!
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vcvt.s32.f32 q13, q13, #16
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vst1.64 {d22-d23},[r0,:128]!
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vsri.32 q12, q0, #16
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vld1.64 {d16-d17},[r3,:128]!
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vsri.32 q13, q1, #16
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vst1.64 {d24-d25},[r0,:128]!
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vcvt.s32.f32 q8, q8, #16
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vld1.64 {d18-d19},[r3,:128]!
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vcvt.s32.f32 q9, q9, #16
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vld1.64 {d20-d21},[r1,:128]!
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vcvt.s32.f32 q10, q10, #16
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vld1.64 {d22-d23},[r1,:128]!
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vcvt.s32.f32 q11, q11, #16
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vst1.64 {d26-d27},[r0,:128]!
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bne 1b
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ands r2, r2, #15
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beq 3f
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2: vsri.32 q10, q8, #16
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vld1.64 {d0-d1}, [r3,:128]!
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vcvt.s32.f32 q0, q0, #16
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vld1.64 {d2-d3}, [r3,:128]!
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vcvt.s32.f32 q1, q1, #16
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vld1.64 {d24-d25},[r1,:128]!
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vcvt.s32.f32 q12, q12, #16
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vsri.32 q11, q9, #16
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vld1.64 {d26-d27},[r1,:128]!
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vcvt.s32.f32 q13, q13, #16
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vst1.64 {d20-d21},[r0,:128]!
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vsri.32 q12, q0, #16
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vst1.64 {d22-d23},[r0,:128]!
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vsri.32 q13, q1, #16
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vst1.64 {d24-d27},[r0,:128]!
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bx lr
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3: vsri.32 q10, q8, #16
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vsri.32 q11, q9, #16
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vst1.64 {d20-d23},[r0,:128]!
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bx lr
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4: push {r4-r8,lr}
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cmp r3, #4
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lsl ip, r3, #1
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blt 4f
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@ 4 channels
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5: ldmia r1!, {r4-r7}
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mov lr, r2
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mov r8, r0
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vld1.64 {d16-d17},[r4,:128]!
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vcvt.s32.f32 q8, q8, #16
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vld1.64 {d18-d19},[r5,:128]!
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vcvt.s32.f32 q9, q9, #16
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vld1.64 {d20-d21},[r6,:128]!
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vcvt.s32.f32 q10, q10, #16
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vld1.64 {d22-d23},[r7,:128]!
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vcvt.s32.f32 q11, q11, #16
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6: subs lr, lr, #8
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vld1.64 {d0-d1}, [r4,:128]!
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vcvt.s32.f32 q0, q0, #16
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vsri.32 q9, q8, #16
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vld1.64 {d2-d3}, [r5,:128]!
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vcvt.s32.f32 q1, q1, #16
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vsri.32 q11, q10, #16
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vld1.64 {d4-d5}, [r6,:128]!
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vcvt.s32.f32 q2, q2, #16
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vzip.32 d18, d22
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vld1.64 {d6-d7}, [r7,:128]!
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vcvt.s32.f32 q3, q3, #16
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vzip.32 d19, d23
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vst1.64 {d18}, [r8], ip
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vsri.32 q1, q0, #16
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vst1.64 {d22}, [r8], ip
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vsri.32 q3, q2, #16
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vst1.64 {d19}, [r8], ip
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vzip.32 d2, d6
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vst1.64 {d23}, [r8], ip
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vzip.32 d3, d7
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beq 7f
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vld1.64 {d16-d17},[r4,:128]!
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vcvt.s32.f32 q8, q8, #16
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vst1.64 {d2}, [r8], ip
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vld1.64 {d18-d19},[r5,:128]!
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vcvt.s32.f32 q9, q9, #16
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vst1.64 {d6}, [r8], ip
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vld1.64 {d20-d21},[r6,:128]!
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vcvt.s32.f32 q10, q10, #16
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vst1.64 {d3}, [r8], ip
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vld1.64 {d22-d23},[r7,:128]!
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vcvt.s32.f32 q11, q11, #16
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vst1.64 {d7}, [r8], ip
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b 6b
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7: vst1.64 {d2}, [r8], ip
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vst1.64 {d6}, [r8], ip
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vst1.64 {d3}, [r8], ip
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vst1.64 {d7}, [r8], ip
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subs r3, r3, #4
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it eq
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popeq {r4-r8,pc}
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cmp r3, #4
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add r0, r0, #8
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bge 5b
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@ 2 channels
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4: cmp r3, #2
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blt 4f
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ldmia r1!, {r4-r5}
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mov lr, r2
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mov r8, r0
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tst lr, #8
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vld1.64 {d16-d17},[r4,:128]!
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vcvt.s32.f32 q8, q8, #16
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vld1.64 {d18-d19},[r5,:128]!
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vcvt.s32.f32 q9, q9, #16
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vld1.64 {d20-d21},[r4,:128]!
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vcvt.s32.f32 q10, q10, #16
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vld1.64 {d22-d23},[r5,:128]!
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vcvt.s32.f32 q11, q11, #16
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beq 6f
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subs lr, lr, #8
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beq 7f
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vsri.32 d18, d16, #16
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vsri.32 d19, d17, #16
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vld1.64 {d16-d17},[r4,:128]!
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vcvt.s32.f32 q8, q8, #16
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vst1.32 {d18[0]}, [r8], ip
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vsri.32 d22, d20, #16
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vst1.32 {d18[1]}, [r8], ip
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vsri.32 d23, d21, #16
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vst1.32 {d19[0]}, [r8], ip
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vst1.32 {d19[1]}, [r8], ip
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vld1.64 {d18-d19},[r5,:128]!
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vcvt.s32.f32 q9, q9, #16
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vst1.32 {d22[0]}, [r8], ip
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vst1.32 {d22[1]}, [r8], ip
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vld1.64 {d20-d21},[r4,:128]!
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vcvt.s32.f32 q10, q10, #16
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vst1.32 {d23[0]}, [r8], ip
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vst1.32 {d23[1]}, [r8], ip
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vld1.64 {d22-d23},[r5,:128]!
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vcvt.s32.f32 q11, q11, #16
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6: subs lr, lr, #16
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vld1.64 {d0-d1}, [r4,:128]!
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vcvt.s32.f32 q0, q0, #16
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vsri.32 d18, d16, #16
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vld1.64 {d2-d3}, [r5,:128]!
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vcvt.s32.f32 q1, q1, #16
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vsri.32 d19, d17, #16
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vld1.64 {d4-d5}, [r4,:128]!
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vcvt.s32.f32 q2, q2, #16
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vld1.64 {d6-d7}, [r5,:128]!
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vcvt.s32.f32 q3, q3, #16
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vst1.32 {d18[0]}, [r8], ip
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vsri.32 d22, d20, #16
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vst1.32 {d18[1]}, [r8], ip
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vsri.32 d23, d21, #16
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vst1.32 {d19[0]}, [r8], ip
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vsri.32 d2, d0, #16
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vst1.32 {d19[1]}, [r8], ip
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vsri.32 d3, d1, #16
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vst1.32 {d22[0]}, [r8], ip
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vsri.32 d6, d4, #16
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vst1.32 {d22[1]}, [r8], ip
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vsri.32 d7, d5, #16
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vst1.32 {d23[0]}, [r8], ip
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vst1.32 {d23[1]}, [r8], ip
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beq 6f
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vld1.64 {d16-d17},[r4,:128]!
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vcvt.s32.f32 q8, q8, #16
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vst1.32 {d2[0]}, [r8], ip
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vst1.32 {d2[1]}, [r8], ip
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vld1.64 {d18-d19},[r5,:128]!
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vcvt.s32.f32 q9, q9, #16
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vst1.32 {d3[0]}, [r8], ip
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vst1.32 {d3[1]}, [r8], ip
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vld1.64 {d20-d21},[r4,:128]!
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vcvt.s32.f32 q10, q10, #16
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vst1.32 {d6[0]}, [r8], ip
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vst1.32 {d6[1]}, [r8], ip
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vld1.64 {d22-d23},[r5,:128]!
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vcvt.s32.f32 q11, q11, #16
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vst1.32 {d7[0]}, [r8], ip
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vst1.32 {d7[1]}, [r8], ip
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bgt 6b
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6: vst1.32 {d2[0]}, [r8], ip
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vst1.32 {d2[1]}, [r8], ip
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vst1.32 {d3[0]}, [r8], ip
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vst1.32 {d3[1]}, [r8], ip
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vst1.32 {d6[0]}, [r8], ip
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vst1.32 {d6[1]}, [r8], ip
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vst1.32 {d7[0]}, [r8], ip
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vst1.32 {d7[1]}, [r8], ip
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b 8f
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7: vsri.32 d18, d16, #16
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vsri.32 d19, d17, #16
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vst1.32 {d18[0]}, [r8], ip
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vsri.32 d22, d20, #16
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vst1.32 {d18[1]}, [r8], ip
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vsri.32 d23, d21, #16
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vst1.32 {d19[0]}, [r8], ip
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vst1.32 {d19[1]}, [r8], ip
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vst1.32 {d22[0]}, [r8], ip
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vst1.32 {d22[1]}, [r8], ip
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vst1.32 {d23[0]}, [r8], ip
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vst1.32 {d23[1]}, [r8], ip
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8: subs r3, r3, #2
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add r0, r0, #4
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it eq
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popeq {r4-r8,pc}
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@ 1 channel
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4: ldr r4, [r1],#4
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tst r2, #8
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mov lr, r2
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mov r5, r0
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vld1.64 {d0-d1}, [r4,:128]!
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vcvt.s32.f32 q0, q0, #16
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vld1.64 {d2-d3}, [r4,:128]!
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vcvt.s32.f32 q1, q1, #16
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bne 8f
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6: subs lr, lr, #16
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vld1.64 {d4-d5}, [r4,:128]!
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vcvt.s32.f32 q2, q2, #16
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vld1.64 {d6-d7}, [r4,:128]!
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vcvt.s32.f32 q3, q3, #16
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vst1.16 {d0[1]}, [r5,:16], ip
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vst1.16 {d0[3]}, [r5,:16], ip
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vst1.16 {d1[1]}, [r5,:16], ip
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vst1.16 {d1[3]}, [r5,:16], ip
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vst1.16 {d2[1]}, [r5,:16], ip
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vst1.16 {d2[3]}, [r5,:16], ip
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vst1.16 {d3[1]}, [r5,:16], ip
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vst1.16 {d3[3]}, [r5,:16], ip
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beq 7f
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vld1.64 {d0-d1}, [r4,:128]!
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vcvt.s32.f32 q0, q0, #16
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vld1.64 {d2-d3}, [r4,:128]!
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vcvt.s32.f32 q1, q1, #16
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7: vst1.16 {d4[1]}, [r5,:16], ip
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vst1.16 {d4[3]}, [r5,:16], ip
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vst1.16 {d5[1]}, [r5,:16], ip
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vst1.16 {d5[3]}, [r5,:16], ip
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vst1.16 {d6[1]}, [r5,:16], ip
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vst1.16 {d6[3]}, [r5,:16], ip
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vst1.16 {d7[1]}, [r5,:16], ip
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vst1.16 {d7[3]}, [r5,:16], ip
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bgt 6b
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pop {r4-r8,pc}
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8: subs lr, lr, #8
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vst1.16 {d0[1]}, [r5,:16], ip
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vst1.16 {d0[3]}, [r5,:16], ip
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vst1.16 {d1[1]}, [r5,:16], ip
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vst1.16 {d1[3]}, [r5,:16], ip
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vst1.16 {d2[1]}, [r5,:16], ip
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vst1.16 {d2[3]}, [r5,:16], ip
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vst1.16 {d3[1]}, [r5,:16], ip
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vst1.16 {d3[3]}, [r5,:16], ip
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it eq
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popeq {r4-r8,pc}
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vld1.64 {d0-d1}, [r4,:128]!
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vcvt.s32.f32 q0, q0, #16
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vld1.64 {d2-d3}, [r4,:128]!
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vcvt.s32.f32 q1, q1, #16
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b 6b
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endfunc
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function ff_int32_to_float_fmul_scalar_neon, export=1
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VFP vdup.32 q0, d0[0]
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VFP len .req r2
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NOVFP vdup.32 q0, r2
|
|
NOVFP len .req r3
|
|
|
|
vld1.32 {q1},[r1,:128]!
|
|
vcvt.f32.s32 q3, q1
|
|
vld1.32 {q2},[r1,:128]!
|
|
vcvt.f32.s32 q8, q2
|
|
1: subs len, len, #8
|
|
pld [r1, #16]
|
|
vmul.f32 q9, q3, q0
|
|
vmul.f32 q10, q8, q0
|
|
beq 2f
|
|
vld1.32 {q1},[r1,:128]!
|
|
vcvt.f32.s32 q3, q1
|
|
vld1.32 {q2},[r1,:128]!
|
|
vcvt.f32.s32 q8, q2
|
|
vst1.32 {q9}, [r0,:128]!
|
|
vst1.32 {q10},[r0,:128]!
|
|
b 1b
|
|
2: vst1.32 {q9}, [r0,:128]!
|
|
vst1.32 {q10},[r0,:128]!
|
|
bx lr
|
|
.unreq len
|
|
endfunc
|