mirror of
https://github.com/xenia-project/FFmpeg.git
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702 lines
25 KiB
ArmAsm
702 lines
25 KiB
ArmAsm
/*
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* ARM NEON optimised DSP functions
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* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "asm.S"
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preserve8
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.fpu neon
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.text
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.macro pixels16 avg=0
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.if \avg
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mov ip, r0
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.endif
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1: vld1.64 {d0, d1}, [r1], r2
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vld1.64 {d2, d3}, [r1], r2
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vld1.64 {d4, d5}, [r1], r2
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pld [r1, r2, lsl #2]
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vld1.64 {d6, d7}, [r1], r2
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pld [r1]
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pld [r1, r2]
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pld [r1, r2, lsl #1]
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.if \avg
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vld1.64 {d16,d17}, [ip], r2
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vrhadd.u8 q0, q0, q8
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vld1.64 {d18,d19}, [ip], r2
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vrhadd.u8 q1, q1, q9
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vld1.64 {d20,d21}, [ip], r2
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vrhadd.u8 q2, q2, q10
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vld1.64 {d22,d23}, [ip], r2
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vrhadd.u8 q3, q3, q11
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.endif
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subs r3, r3, #4
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vst1.64 {d0, d1}, [r0,:128], r2
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vst1.64 {d2, d3}, [r0,:128], r2
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vst1.64 {d4, d5}, [r0,:128], r2
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vst1.64 {d6, d7}, [r0,:128], r2
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bne 1b
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bx lr
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.endm
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.macro pixels16_x2 vhadd=vrhadd.u8
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1: vld1.64 {d0-d2}, [r1], r2
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vld1.64 {d4-d6}, [r1], r2
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pld [r1]
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pld [r1, r2]
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subs r3, r3, #2
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vext.8 q1, q0, q1, #1
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\vhadd q0, q0, q1
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vext.8 q3, q2, q3, #1
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\vhadd q2, q2, q3
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vst1.64 {d0, d1}, [r0,:128], r2
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vst1.64 {d4, d5}, [r0,:128], r2
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bne 1b
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bx lr
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.endm
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.macro pixels16_y2 vhadd=vrhadd.u8
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push {lr}
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add ip, r1, r2
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lsl lr, r2, #1
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vld1.64 {d0, d1}, [r1], lr
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vld1.64 {d2, d3}, [ip], lr
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1: subs r3, r3, #2
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\vhadd q2, q0, q1
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vld1.64 {d0, d1}, [r1], lr
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\vhadd q3, q0, q1
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vld1.64 {d2, d3}, [ip], lr
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pld [r1]
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pld [ip]
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vst1.64 {d4, d5}, [r0,:128], r2
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vst1.64 {d6, d7}, [r0,:128], r2
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bne 1b
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pop {pc}
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.endm
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.macro pixels16_xy2 vshrn=vrshrn.u16 no_rnd=0
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push {lr}
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lsl lr, r2, #1
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add ip, r1, r2
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vld1.64 {d0-d2}, [r1], lr
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vld1.64 {d4-d6}, [ip], lr
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.if \no_rnd
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vmov.i16 q13, #1
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.endif
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pld [r1]
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pld [ip]
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vext.8 q1, q0, q1, #1
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vext.8 q3, q2, q3, #1
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vaddl.u8 q8, d0, d2
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vaddl.u8 q10, d1, d3
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vaddl.u8 q9, d4, d6
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vaddl.u8 q11, d5, d7
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1: subs r3, r3, #2
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vld1.64 {d0-d2}, [r1], lr
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vadd.u16 q12, q8, q9
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pld [r1]
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.if \no_rnd
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vadd.u16 q12, q12, q13
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.endif
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vext.8 q15, q0, q1, #1
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vadd.u16 q1 , q10, q11
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\vshrn d28, q12, #2
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.if \no_rnd
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vadd.u16 q1, q1, q13
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.endif
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\vshrn d29, q1, #2
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vaddl.u8 q8, d0, d30
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vld1.64 {d2-d4}, [ip], lr
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vaddl.u8 q10, d1, d31
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vst1.64 {d28,d29}, [r0,:128], r2
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vadd.u16 q12, q8, q9
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pld [ip]
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.if \no_rnd
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vadd.u16 q12, q12, q13
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.endif
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vext.8 q2, q1, q2, #1
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vadd.u16 q0, q10, q11
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\vshrn d30, q12, #2
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.if \no_rnd
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vadd.u16 q0, q0, q13
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.endif
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\vshrn d31, q0, #2
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vaddl.u8 q9, d2, d4
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vaddl.u8 q11, d3, d5
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vst1.64 {d30,d31}, [r0,:128], r2
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bgt 1b
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pop {pc}
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.endm
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.macro pixels8
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1: vld1.64 {d0}, [r1], r2
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vld1.64 {d1}, [r1], r2
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vld1.64 {d2}, [r1], r2
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pld [r1, r2, lsl #2]
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vld1.64 {d3}, [r1], r2
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pld [r1]
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pld [r1, r2]
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pld [r1, r2, lsl #1]
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subs r3, r3, #4
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vst1.64 {d0}, [r0,:64], r2
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vst1.64 {d1}, [r0,:64], r2
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vst1.64 {d2}, [r0,:64], r2
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vst1.64 {d3}, [r0,:64], r2
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bne 1b
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bx lr
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.endm
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.macro pixels8_x2 vhadd=vrhadd.u8
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1: vld1.64 {d0, d1}, [r1], r2
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vext.8 d1, d0, d1, #1
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vld1.64 {d2, d3}, [r1], r2
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vext.8 d3, d2, d3, #1
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pld [r1]
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pld [r1, r2]
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subs r3, r3, #2
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vswp d1, d2
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\vhadd q0, q0, q1
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vst1.64 {d0}, [r0,:64], r2
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vst1.64 {d1}, [r0,:64], r2
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bne 1b
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bx lr
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.endm
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.macro pixels8_y2 vhadd=vrhadd.u8
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push {lr}
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add ip, r1, r2
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lsl lr, r2, #1
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vld1.64 {d0}, [r1], lr
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vld1.64 {d1}, [ip], lr
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1: subs r3, r3, #2
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\vhadd d4, d0, d1
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vld1.64 {d0}, [r1], lr
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\vhadd d5, d0, d1
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vld1.64 {d1}, [ip], lr
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pld [r1]
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pld [ip]
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vst1.64 {d4}, [r0,:64], r2
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vst1.64 {d5}, [r0,:64], r2
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bne 1b
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pop {pc}
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.endm
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.macro pixels8_xy2 vshrn=vrshrn.u16 no_rnd=0
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push {lr}
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lsl lr, r2, #1
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add ip, r1, r2
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vld1.64 {d0, d1}, [r1], lr
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vld1.64 {d2, d3}, [ip], lr
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.if \no_rnd
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vmov.i16 q11, #1
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.endif
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pld [r1]
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pld [ip]
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vext.8 d4, d0, d1, #1
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vext.8 d6, d2, d3, #1
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vaddl.u8 q8, d0, d4
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vaddl.u8 q9, d2, d6
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1: subs r3, r3, #2
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vld1.64 {d0, d1}, [r1], lr
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pld [r1]
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vadd.u16 q10, q8, q9
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vext.8 d4, d0, d1, #1
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.if \no_rnd
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vadd.u16 q10, q10, q11
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.endif
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vaddl.u8 q8, d0, d4
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\vshrn d5, q10, #2
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vld1.64 {d2, d3}, [ip], lr
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vadd.u16 q10, q8, q9
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pld [ip]
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.if \no_rnd
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vadd.u16 q10, q10, q11
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.endif
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vst1.64 {d5}, [r0,:64], r2
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\vshrn d7, q10, #2
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vext.8 d6, d2, d3, #1
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vaddl.u8 q9, d2, d6
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vst1.64 {d7}, [r0,:64], r2
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bgt 1b
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pop {pc}
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.endm
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.macro pixfunc pfx name suf rnd_op args:vararg
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function ff_\pfx\name\suf\()_neon, export=1
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\name \rnd_op \args
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.endfunc
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.endm
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.macro pixfunc2 pfx name args:vararg
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pixfunc \pfx \name
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pixfunc \pfx \name \args
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.endm
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function ff_put_h264_qpel16_mc00_neon, export=1
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mov r3, #16
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.endfunc
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pixfunc put_ pixels16
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pixfunc2 put_ pixels16_x2, _no_rnd, vhadd.u8
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pixfunc2 put_ pixels16_y2, _no_rnd, vhadd.u8
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pixfunc2 put_ pixels16_xy2, _no_rnd, vshrn.u16, 1
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function ff_avg_h264_qpel16_mc00_neon, export=1
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mov r3, #16
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.endfunc
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pixfunc avg_ pixels16,, 1
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function ff_put_h264_qpel8_mc00_neon, export=1
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mov r3, #8
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.endfunc
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pixfunc put_ pixels8
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pixfunc2 put_ pixels8_x2, _no_rnd, vhadd.u8
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pixfunc2 put_ pixels8_y2, _no_rnd, vhadd.u8
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pixfunc2 put_ pixels8_xy2, _no_rnd, vshrn.u16, 1
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function ff_float_to_int16_neon, export=1
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subs r2, r2, #8
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vld1.64 {d0-d1}, [r1,:128]!
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vcvt.s32.f32 q8, q0, #16
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vld1.64 {d2-d3}, [r1,:128]!
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vcvt.s32.f32 q9, q1, #16
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beq 3f
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bics ip, r2, #15
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beq 2f
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1: subs ip, ip, #16
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vshrn.s32 d4, q8, #16
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vld1.64 {d0-d1}, [r1,:128]!
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vcvt.s32.f32 q0, q0, #16
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vshrn.s32 d5, q9, #16
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vld1.64 {d2-d3}, [r1,:128]!
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vcvt.s32.f32 q1, q1, #16
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vshrn.s32 d6, q0, #16
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vst1.64 {d4-d5}, [r0,:128]!
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vshrn.s32 d7, q1, #16
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vld1.64 {d16-d17},[r1,:128]!
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vcvt.s32.f32 q8, q8, #16
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vld1.64 {d18-d19},[r1,:128]!
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vcvt.s32.f32 q9, q9, #16
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vst1.64 {d6-d7}, [r0,:128]!
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bne 1b
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ands r2, r2, #15
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beq 3f
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2: vld1.64 {d0-d1}, [r1,:128]!
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vshrn.s32 d4, q8, #16
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vcvt.s32.f32 q0, q0, #16
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vld1.64 {d2-d3}, [r1,:128]!
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vshrn.s32 d5, q9, #16
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vcvt.s32.f32 q1, q1, #16
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vshrn.s32 d6, q0, #16
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vst1.64 {d4-d5}, [r0,:128]!
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vshrn.s32 d7, q1, #16
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vst1.64 {d6-d7}, [r0,:128]!
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bx lr
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3: vshrn.s32 d4, q8, #16
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vshrn.s32 d5, q9, #16
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vst1.64 {d4-d5}, [r0,:128]!
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bx lr
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.endfunc
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function ff_float_to_int16_interleave_neon, export=1
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cmp r3, #2
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ldrlt r1, [r1]
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blt ff_float_to_int16_neon
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bne 4f
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ldr r3, [r1]
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ldr r1, [r1, #4]
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subs r2, r2, #8
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vld1.64 {d0-d1}, [r3,:128]!
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vcvt.s32.f32 q8, q0, #16
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vld1.64 {d2-d3}, [r3,:128]!
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vcvt.s32.f32 q9, q1, #16
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vld1.64 {d20-d21},[r1,:128]!
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vcvt.s32.f32 q10, q10, #16
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vld1.64 {d22-d23},[r1,:128]!
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vcvt.s32.f32 q11, q11, #16
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beq 3f
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bics ip, r2, #15
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beq 2f
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1: subs ip, ip, #16
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vld1.64 {d0-d1}, [r3,:128]!
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vcvt.s32.f32 q0, q0, #16
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vsri.32 q10, q8, #16
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vld1.64 {d2-d3}, [r3,:128]!
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vcvt.s32.f32 q1, q1, #16
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vld1.64 {d24-d25},[r1,:128]!
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vcvt.s32.f32 q12, q12, #16
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vld1.64 {d26-d27},[r1,:128]!
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vsri.32 q11, q9, #16
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vst1.64 {d20-d21},[r0,:128]!
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vcvt.s32.f32 q13, q13, #16
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vst1.64 {d22-d23},[r0,:128]!
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vsri.32 q12, q0, #16
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vld1.64 {d16-d17},[r3,:128]!
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vsri.32 q13, q1, #16
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vst1.64 {d24-d25},[r0,:128]!
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vcvt.s32.f32 q8, q8, #16
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vld1.64 {d18-d19},[r3,:128]!
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vcvt.s32.f32 q9, q9, #16
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vld1.64 {d20-d21},[r1,:128]!
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vcvt.s32.f32 q10, q10, #16
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vld1.64 {d22-d23},[r1,:128]!
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vcvt.s32.f32 q11, q11, #16
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vst1.64 {d26-d27},[r0,:128]!
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bne 1b
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ands r2, r2, #15
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beq 3f
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2: vsri.32 q10, q8, #16
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vld1.64 {d0-d1}, [r3,:128]!
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vcvt.s32.f32 q0, q0, #16
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vld1.64 {d2-d3}, [r3,:128]!
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vcvt.s32.f32 q1, q1, #16
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vld1.64 {d24-d25},[r1,:128]!
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vcvt.s32.f32 q12, q12, #16
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vsri.32 q11, q9, #16
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vld1.64 {d26-d27},[r1,:128]!
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vcvt.s32.f32 q13, q13, #16
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vst1.64 {d20-d21},[r0,:128]!
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vsri.32 q12, q0, #16
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vst1.64 {d22-d23},[r0,:128]!
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vsri.32 q13, q1, #16
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vst1.64 {d24-d27},[r0,:128]!
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bx lr
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3: vsri.32 q10, q8, #16
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vsri.32 q11, q9, #16
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vst1.64 {d20-d23},[r0,:128]!
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bx lr
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4: push {r4-r8,lr}
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cmp r3, #4
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lsl ip, r3, #1
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blt 4f
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@ 4 channels
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5: ldmia r1!, {r4-r7}
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mov lr, r2
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mov r8, r0
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vld1.64 {d16-d17},[r4,:128]!
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vcvt.s32.f32 q8, q8, #16
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vld1.64 {d18-d19},[r5,:128]!
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vcvt.s32.f32 q9, q9, #16
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vld1.64 {d20-d21},[r6,:128]!
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vcvt.s32.f32 q10, q10, #16
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vld1.64 {d22-d23},[r7,:128]!
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vcvt.s32.f32 q11, q11, #16
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6: subs lr, lr, #8
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vld1.64 {d0-d1}, [r4,:128]!
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vcvt.s32.f32 q0, q0, #16
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vsri.32 q9, q8, #16
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vld1.64 {d2-d3}, [r5,:128]!
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vcvt.s32.f32 q1, q1, #16
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vsri.32 q11, q10, #16
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vld1.64 {d4-d5}, [r6,:128]!
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vcvt.s32.f32 q2, q2, #16
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vzip.32 d18, d22
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vld1.64 {d6-d7}, [r7,:128]!
|
|
vcvt.s32.f32 q3, q3, #16
|
|
vzip.32 d19, d23
|
|
vst1.64 {d18}, [r8], ip
|
|
vsri.32 q1, q0, #16
|
|
vst1.64 {d22}, [r8], ip
|
|
vsri.32 q3, q2, #16
|
|
vst1.64 {d19}, [r8], ip
|
|
vzip.32 d2, d6
|
|
vst1.64 {d23}, [r8], ip
|
|
vzip.32 d3, d7
|
|
beq 7f
|
|
vld1.64 {d16-d17},[r4,:128]!
|
|
vcvt.s32.f32 q8, q8, #16
|
|
vst1.64 {d2}, [r8], ip
|
|
vld1.64 {d18-d19},[r5,:128]!
|
|
vcvt.s32.f32 q9, q9, #16
|
|
vst1.64 {d6}, [r8], ip
|
|
vld1.64 {d20-d21},[r6,:128]!
|
|
vcvt.s32.f32 q10, q10, #16
|
|
vst1.64 {d3}, [r8], ip
|
|
vld1.64 {d22-d23},[r7,:128]!
|
|
vcvt.s32.f32 q11, q11, #16
|
|
vst1.64 {d7}, [r8], ip
|
|
b 6b
|
|
7: vst1.64 {d2}, [r8], ip
|
|
vst1.64 {d6}, [r8], ip
|
|
vst1.64 {d3}, [r8], ip
|
|
vst1.64 {d7}, [r8], ip
|
|
subs r3, r3, #4
|
|
popeq {r4-r8,pc}
|
|
cmp r3, #4
|
|
add r0, r0, #8
|
|
bge 5b
|
|
|
|
@ 2 channels
|
|
4: cmp r3, #2
|
|
blt 4f
|
|
ldmia r1!, {r4-r5}
|
|
mov lr, r2
|
|
mov r8, r0
|
|
tst lr, #8
|
|
vld1.64 {d16-d17},[r4,:128]!
|
|
vcvt.s32.f32 q8, q8, #16
|
|
vld1.64 {d18-d19},[r5,:128]!
|
|
vcvt.s32.f32 q9, q9, #16
|
|
vld1.64 {d20-d21},[r4,:128]!
|
|
vcvt.s32.f32 q10, q10, #16
|
|
vld1.64 {d22-d23},[r5,:128]!
|
|
vcvt.s32.f32 q11, q11, #16
|
|
beq 6f
|
|
subs lr, lr, #8
|
|
beq 7f
|
|
vsri.32 d18, d16, #16
|
|
vsri.32 d19, d17, #16
|
|
vld1.64 {d16-d17},[r4,:128]!
|
|
vcvt.s32.f32 q8, q8, #16
|
|
vst1.32 {d18[0]}, [r8], ip
|
|
vsri.32 d22, d20, #16
|
|
vst1.32 {d18[1]}, [r8], ip
|
|
vsri.32 d23, d21, #16
|
|
vst1.32 {d19[0]}, [r8], ip
|
|
vst1.32 {d19[1]}, [r8], ip
|
|
vld1.64 {d18-d19},[r5,:128]!
|
|
vcvt.s32.f32 q9, q9, #16
|
|
vst1.32 {d22[0]}, [r8], ip
|
|
vst1.32 {d22[1]}, [r8], ip
|
|
vld1.64 {d20-d21},[r4,:128]!
|
|
vcvt.s32.f32 q10, q10, #16
|
|
vst1.32 {d23[0]}, [r8], ip
|
|
vst1.32 {d23[1]}, [r8], ip
|
|
vld1.64 {d22-d23},[r5,:128]!
|
|
vcvt.s32.f32 q11, q11, #16
|
|
6: subs lr, lr, #16
|
|
vld1.64 {d0-d1}, [r4,:128]!
|
|
vcvt.s32.f32 q0, q0, #16
|
|
vsri.32 d18, d16, #16
|
|
vld1.64 {d2-d3}, [r5,:128]!
|
|
vcvt.s32.f32 q1, q1, #16
|
|
vsri.32 d19, d17, #16
|
|
vld1.64 {d4-d5}, [r4,:128]!
|
|
vcvt.s32.f32 q2, q2, #16
|
|
vld1.64 {d6-d7}, [r5,:128]!
|
|
vcvt.s32.f32 q3, q3, #16
|
|
vst1.32 {d18[0]}, [r8], ip
|
|
vsri.32 d22, d20, #16
|
|
vst1.32 {d18[1]}, [r8], ip
|
|
vsri.32 d23, d21, #16
|
|
vst1.32 {d19[0]}, [r8], ip
|
|
vsri.32 d2, d0, #16
|
|
vst1.32 {d19[1]}, [r8], ip
|
|
vsri.32 d3, d1, #16
|
|
vst1.32 {d22[0]}, [r8], ip
|
|
vsri.32 d6, d4, #16
|
|
vst1.32 {d22[1]}, [r8], ip
|
|
vsri.32 d7, d5, #16
|
|
vst1.32 {d23[0]}, [r8], ip
|
|
vst1.32 {d23[1]}, [r8], ip
|
|
beq 6f
|
|
vld1.64 {d16-d17},[r4,:128]!
|
|
vcvt.s32.f32 q8, q8, #16
|
|
vst1.32 {d2[0]}, [r8], ip
|
|
vst1.32 {d2[1]}, [r8], ip
|
|
vld1.64 {d18-d19},[r5,:128]!
|
|
vcvt.s32.f32 q9, q9, #16
|
|
vst1.32 {d3[0]}, [r8], ip
|
|
vst1.32 {d3[1]}, [r8], ip
|
|
vld1.64 {d20-d21},[r4,:128]!
|
|
vcvt.s32.f32 q10, q10, #16
|
|
vst1.32 {d6[0]}, [r8], ip
|
|
vst1.32 {d6[1]}, [r8], ip
|
|
vld1.64 {d22-d23},[r5,:128]!
|
|
vcvt.s32.f32 q11, q11, #16
|
|
vst1.32 {d7[0]}, [r8], ip
|
|
vst1.32 {d7[1]}, [r8], ip
|
|
bgt 6b
|
|
6: vst1.32 {d2[0]}, [r8], ip
|
|
vst1.32 {d2[1]}, [r8], ip
|
|
vst1.32 {d3[0]}, [r8], ip
|
|
vst1.32 {d3[1]}, [r8], ip
|
|
vst1.32 {d6[0]}, [r8], ip
|
|
vst1.32 {d6[1]}, [r8], ip
|
|
vst1.32 {d7[0]}, [r8], ip
|
|
vst1.32 {d7[1]}, [r8], ip
|
|
b 8f
|
|
7: vsri.32 d18, d16, #16
|
|
vsri.32 d19, d17, #16
|
|
vst1.32 {d18[0]}, [r8], ip
|
|
vsri.32 d22, d20, #16
|
|
vst1.32 {d18[1]}, [r8], ip
|
|
vsri.32 d23, d21, #16
|
|
vst1.32 {d19[0]}, [r8], ip
|
|
vst1.32 {d19[1]}, [r8], ip
|
|
vst1.32 {d22[0]}, [r8], ip
|
|
vst1.32 {d22[1]}, [r8], ip
|
|
vst1.32 {d23[0]}, [r8], ip
|
|
vst1.32 {d23[1]}, [r8], ip
|
|
8: subs r3, r3, #2
|
|
add r0, r0, #4
|
|
popeq {r4-r8,pc}
|
|
|
|
@ 1 channel
|
|
4: ldr r4, [r1],#4
|
|
tst r2, #8
|
|
mov lr, r2
|
|
mov r5, r0
|
|
vld1.64 {d0-d1}, [r4,:128]!
|
|
vcvt.s32.f32 q0, q0, #16
|
|
vld1.64 {d2-d3}, [r4,:128]!
|
|
vcvt.s32.f32 q1, q1, #16
|
|
bne 8f
|
|
6: subs lr, lr, #16
|
|
vld1.64 {d4-d5}, [r4,:128]!
|
|
vcvt.s32.f32 q2, q2, #16
|
|
vld1.64 {d6-d7}, [r4,:128]!
|
|
vcvt.s32.f32 q3, q3, #16
|
|
vst1.16 {d0[1]}, [r5,:16], ip
|
|
vst1.16 {d0[3]}, [r5,:16], ip
|
|
vst1.16 {d1[1]}, [r5,:16], ip
|
|
vst1.16 {d1[3]}, [r5,:16], ip
|
|
vst1.16 {d2[1]}, [r5,:16], ip
|
|
vst1.16 {d2[3]}, [r5,:16], ip
|
|
vst1.16 {d3[1]}, [r5,:16], ip
|
|
vst1.16 {d3[3]}, [r5,:16], ip
|
|
beq 7f
|
|
vld1.64 {d0-d1}, [r4,:128]!
|
|
vcvt.s32.f32 q0, q0, #16
|
|
vld1.64 {d2-d3}, [r4,:128]!
|
|
vcvt.s32.f32 q1, q1, #16
|
|
7: vst1.16 {d4[1]}, [r5,:16], ip
|
|
vst1.16 {d4[3]}, [r5,:16], ip
|
|
vst1.16 {d5[1]}, [r5,:16], ip
|
|
vst1.16 {d5[3]}, [r5,:16], ip
|
|
vst1.16 {d6[1]}, [r5,:16], ip
|
|
vst1.16 {d6[3]}, [r5,:16], ip
|
|
vst1.16 {d7[1]}, [r5,:16], ip
|
|
vst1.16 {d7[3]}, [r5,:16], ip
|
|
bgt 6b
|
|
pop {r4-r8,pc}
|
|
8: subs lr, lr, #8
|
|
vst1.16 {d0[1]}, [r5,:16], ip
|
|
vst1.16 {d0[3]}, [r5,:16], ip
|
|
vst1.16 {d1[1]}, [r5,:16], ip
|
|
vst1.16 {d1[3]}, [r5,:16], ip
|
|
vst1.16 {d2[1]}, [r5,:16], ip
|
|
vst1.16 {d2[3]}, [r5,:16], ip
|
|
vst1.16 {d3[1]}, [r5,:16], ip
|
|
vst1.16 {d3[3]}, [r5,:16], ip
|
|
popeq {r4-r8,pc}
|
|
vld1.64 {d0-d1}, [r4,:128]!
|
|
vcvt.s32.f32 q0, q0, #16
|
|
vld1.64 {d2-d3}, [r4,:128]!
|
|
vcvt.s32.f32 q1, q1, #16
|
|
b 6b
|
|
.endfunc
|
|
|
|
function ff_vector_fmul_neon, export=1
|
|
mov r3, r0
|
|
subs r2, r2, #8
|
|
vld1.64 {d0-d3}, [r0,:128]!
|
|
vld1.64 {d4-d7}, [r1,:128]!
|
|
vmul.f32 q8, q0, q2
|
|
vmul.f32 q9, q1, q3
|
|
beq 3f
|
|
bics ip, r2, #15
|
|
beq 2f
|
|
1: subs ip, ip, #16
|
|
vld1.64 {d0-d1}, [r0,:128]!
|
|
vld1.64 {d4-d5}, [r1,:128]!
|
|
vmul.f32 q10, q0, q2
|
|
vld1.64 {d2-d3}, [r0,:128]!
|
|
vld1.64 {d6-d7}, [r1,:128]!
|
|
vmul.f32 q11, q1, q3
|
|
vst1.64 {d16-d19},[r3,:128]!
|
|
vld1.64 {d0-d1}, [r0,:128]!
|
|
vld1.64 {d4-d5}, [r1,:128]!
|
|
vmul.f32 q8, q0, q2
|
|
vld1.64 {d2-d3}, [r0,:128]!
|
|
vld1.64 {d6-d7}, [r1,:128]!
|
|
vmul.f32 q9, q1, q3
|
|
vst1.64 {d20-d23},[r3,:128]!
|
|
bne 1b
|
|
ands r2, r2, #15
|
|
beq 3f
|
|
2: vld1.64 {d0-d1}, [r0,:128]!
|
|
vld1.64 {d4-d5}, [r1,:128]!
|
|
vst1.64 {d16-d17},[r3,:128]!
|
|
vmul.f32 q8, q0, q2
|
|
vld1.64 {d2-d3}, [r0,:128]!
|
|
vld1.64 {d6-d7}, [r1,:128]!
|
|
vst1.64 {d18-d19},[r3,:128]!
|
|
vmul.f32 q9, q1, q3
|
|
3: vst1.64 {d16-d19},[r3,:128]!
|
|
bx lr
|
|
.endfunc
|
|
|
|
function ff_vector_fmul_window_neon, export=1
|
|
vld1.32 {d16[],d17[]}, [sp,:32]
|
|
push {r4,r5,lr}
|
|
ldr lr, [sp, #16]
|
|
sub r2, r2, #8
|
|
sub r5, lr, #2
|
|
add r2, r2, r5, lsl #2
|
|
add r4, r3, r5, lsl #3
|
|
add ip, r0, r5, lsl #3
|
|
mov r5, #-16
|
|
vld1.64 {d0,d1}, [r1,:128]!
|
|
vld1.64 {d2,d3}, [r2,:128], r5
|
|
vld1.64 {d4,d5}, [r3,:128]!
|
|
vld1.64 {d6,d7}, [r4,:128], r5
|
|
1: subs lr, lr, #4
|
|
vmov q11, q8
|
|
vmla.f32 d22, d0, d4
|
|
vmov q10, q8
|
|
vmla.f32 d23, d1, d5
|
|
vrev64.32 q3, q3
|
|
vmla.f32 d20, d0, d7
|
|
vrev64.32 q1, q1
|
|
vmla.f32 d21, d1, d6
|
|
beq 2f
|
|
vmla.f32 d22, d3, d7
|
|
vld1.64 {d0,d1}, [r1,:128]!
|
|
vmla.f32 d23, d2, d6
|
|
vld1.64 {d18,d19},[r2,:128], r5
|
|
vmls.f32 d20, d3, d4
|
|
vld1.64 {d24,d25},[r3,:128]!
|
|
vmls.f32 d21, d2, d5
|
|
vld1.64 {d6,d7}, [r4,:128], r5
|
|
vmov q1, q9
|
|
vrev64.32 q11, q11
|
|
vmov q2, q12
|
|
vswp d22, d23
|
|
vst1.64 {d20,d21},[r0,:128]!
|
|
vst1.64 {d22,d23},[ip,:128], r5
|
|
b 1b
|
|
2: vmla.f32 d22, d3, d7
|
|
vmla.f32 d23, d2, d6
|
|
vmls.f32 d20, d3, d4
|
|
vmls.f32 d21, d2, d5
|
|
vrev64.32 q11, q11
|
|
vswp d22, d23
|
|
vst1.64 {d20,d21},[r0,:128]!
|
|
vst1.64 {d22,d23},[ip,:128], r5
|
|
pop {r4,r5,pc}
|
|
.endfunc
|