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Vulkan: Host writes are implicitly flushed on submit.
Use TOP_OF_PIPE/0 access instead to work around spammy asserts on Anvil. We still have to invalidate the caches however.
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@ -444,8 +444,8 @@ struct vk_texture vulkan_create_texture(vk_t *vk,
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vulkan_image_layout_transition(vk, staging, tmp.image,
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VK_IMAGE_LAYOUT_PREINITIALIZED, VK_IMAGE_LAYOUT_GENERAL,
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VK_ACCESS_HOST_WRITE_BIT, VK_ACCESS_TRANSFER_READ_BIT,
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VK_PIPELINE_STAGE_HOST_BIT,
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0, VK_ACCESS_TRANSFER_READ_BIT,
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VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
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VK_PIPELINE_STAGE_TRANSFER_BIT);
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vulkan_image_layout_transition(vk, staging, tex.image,
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@ -565,16 +565,16 @@ void vulkan_transition_texture(vk_t *vk, struct vk_texture *texture)
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case VULKAN_TEXTURE_STREAMED:
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vulkan_image_layout_transition(vk, vk->cmd, texture->image,
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texture->layout, VK_IMAGE_LAYOUT_GENERAL,
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VK_ACCESS_HOST_WRITE_BIT, VK_ACCESS_SHADER_READ_BIT,
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VK_PIPELINE_STAGE_HOST_BIT,
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0, VK_ACCESS_SHADER_READ_BIT,
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VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
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VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT);
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break;
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case VULKAN_TEXTURE_STAGING:
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vulkan_image_layout_transition(vk, vk->cmd, texture->image,
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texture->layout, VK_IMAGE_LAYOUT_GENERAL,
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VK_ACCESS_HOST_WRITE_BIT, VK_ACCESS_TRANSFER_READ_BIT,
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VK_PIPELINE_STAGE_HOST_BIT,
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0, VK_ACCESS_TRANSFER_READ_BIT,
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VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
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VK_PIPELINE_STAGE_TRANSFER_BIT);
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break;
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@ -1354,11 +1354,11 @@ static void vulkan_readback(vk_t *vk)
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static void vulkan_flush_caches(vk_t *vk)
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{
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VkMemoryBarrier barrier = { VK_STRUCTURE_TYPE_MEMORY_BARRIER };
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barrier.srcAccessMask = VK_ACCESS_HOST_WRITE_BIT;
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barrier.srcAccessMask = 0;
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barrier.dstAccessMask = VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT | VK_ACCESS_UNIFORM_READ_BIT;
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VKFUNC(vkCmdPipelineBarrier)(vk->cmd,
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VK_PIPELINE_STAGE_HOST_BIT,
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VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
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VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
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VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
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VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT,
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