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cpulib: Add ISBs or comment why they are unneeded

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Change-Id: I18a41bb9fedda635c3c002a7f112578808410ef6
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
This commit is contained in:
Dimitris Papastamos 2018-06-07 13:20:19 +01:00
parent ac0197d9d5
commit bd5a76ac7c
4 changed files with 4 additions and 0 deletions
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1
lib/cpus/aarch64/cortex_a57.S
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@ -404,6 +404,7 @@ func cortex_a57_reset_func
#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
adr x0, wa_cve_2017_5715_mmu_vbar
msr vbar_el3, x0
/* isb will be performed before returning from this function */
#endif
#if WORKAROUND_CVE_2018_3639

1
lib/cpus/aarch64/cortex_a72.S
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@ -137,6 +137,7 @@ func cortex_a72_reset_func
cpu_check_csv2 x0, 1f
adr x0, wa_cve_2017_5715_mmu_vbar
msr vbar_el3, x0
/* isb will be performed before returning from this function */
1:
#endif

1
lib/cpus/aarch64/cortex_a73.S
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@ -40,6 +40,7 @@ func cortex_a73_reset_func
cpu_check_csv2 x0, 1f
adr x0, wa_cve_2017_5715_bpiall_vbar
msr vbar_el3, x0
/* isb will be performed before returning from this function */
1:
#endif

1
lib/cpus/aarch64/cortex_a75.S
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@ -15,6 +15,7 @@ func cortex_a75_reset_func
cpu_check_csv2 x0, 1f
adr x0, wa_cve_2017_5715_bpiall_vbar
msr vbar_el3, x0
isb
1:
#endif