When TF-A is built with RESET_TO_BL31=1 option, BL31 is the
first image to be run and should have all the memory allocated
to it except for the memory reserved for Shared RAM at the start
of Trusted SRAM.
This patch fixes FVP BL31 load address and its image size for
RESET_TO_BL31=1 option. BL31 startup address should be set to
0x400_1000 and its maximum image size to the size of Trusted SRAM
minus the first 4KB of shared memory.
Loading BL31 at 0x0402_0000 as it is currently stated in
'\docs\plat\arm\fvp\index.rst' causes EL3 exception when the
image size gets increased (i.e. building with LOG_LEVEL=50)
but doesn't exceed 0x3B000 not causing build error.
Change-Id: Ie450baaf247f1577112f8d143b24e76c39d33e91
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
The TBBR implementation extracts hashes from certificates and stores
them in static buffers. TF-A supports 3 variants of SHA right now:
SHA-256, SHA-384 and SHA-512. When support for SHA-512 was added in
commit 9a3088a5f509084e60d9c55bf53985c5ec4ca821 ("tbbr: Add build flag
HASH_ALG to let the user to select the SHA"), the hash buffers got
unconditionally increased from 51 to 83 bytes each. We can reduce that
space if we're using SHA-256 or SHA-384.
This saves some BSS space in both BL1 and BL2:
- BL1 with SHA-256: saving 168 bytes.
- BL1 with SHA-384: saving 80 bytes.
- BL2 with SHA-256: saving 384 bytes.
- BL2 with SHA-384: saving 192 bytes.
Change-Id: I0d02e5dc5f0162e82339c768609c9766cfe7e2bd
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
The TBBR implementation extracts public keys from certificates and
stores them in static buffers. DER-encoded ECDSA keys are only 91 bytes
each but were each allocated 294 bytes instead. Reducing the size of
these buffers saves 609 bytes of BSS in BL2 (294 - 91 = 203 bytes for
each of the 3 key buffers in use).
Also add a comment claryfing that key buffers are tailored on RSA key
sizes when both ECDSA and RSA keys are used.
Change-Id: Iad332856e7af1f9814418d012fba3e1e9399f72a
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Adding support for 32MHz UART clock and selecting it as the
default UART clock
Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Running checkpatch.pl on the codebase and making required changes
Change-Id: I7d3f8764cef632ab2a6d3c355c68f590440b85b8
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Note: This patch implements in-band messaging protocol only.
ARM has launched a next version of MHU i.e. MHUv2 with its latest
subsystems. The main change is that the MHUv2 is now a distributed IP
with different peripheral views (registers) for the sender and receiver.
Another main difference is that MHUv1 duplex channels are now split into
simplex/half duplex in MHUv2. MHUv2 has a configurable number of
communication channels. There is a capability register (MSG_NO_CAP) to
find out how many channels are available in a system.
The register offsets have also changed for STAT, SET & CLEAR registers
from 0x0, 0x8 & 0x10 in MHUv1 to 0x0, 0xC & 0x8 in MHUv2 respectively.
0x0 0x4 0x8 0xC 0x1F
------------------------....-----
| STAT | | | SET | | |
------------------------....-----
Transmit Channel
0x0 0x4 0x8 0xC 0x1F
------------------------....-----
| STAT | | CLR | | | |
------------------------....-----
Receive Channel
The MHU controller can request the receiver to wake-up and once the
request is removed, the receiver may go back to sleep, but the MHU
itself does not actively put a receiver to sleep.
So, in order to wake-up the receiver when the sender wants to send data,
the sender has to set ACCESS_REQUEST register first in order to wake-up
receiver, state of which can be detected using ACCESS_READY register.
ACCESS_REQUEST has an offset of 0xF88 & ACCESS_READY has an offset
of 0xF8C and are accessible only on any sender channel.
This patch adds necessary changes in a new file required to support the
latest MHUv2 controller. This patch also needs an update in DT binding
for ARM MHUv2 as we need a second register base (tx base) which would
be used as the send channel base.
Change-Id: I1455e08b3d88671a191c558790c503eabe07a8e6
Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
In extreme cases, the number of secure regions is one more than
non-secure regions. So array "s_base" and "s_top"s size
in struct param_ddr_usage need to be adjust to "DDR_REGION_NR_MAX + 1".
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ifc09da2c8f8afa1aebcc78f8fbc21ac95abdece2
Use space after #define consistently, drop useless parenthesis,
no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I72846d8672cab09b128e3118f4b7042a5a9c0df5
This patch changes the destination address of BL31 and BL32 From
fixed address for getting from the each certificates.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream rework
Change-Id: Ide11776feff25e6fdd55ab28503a15b658b2e0d5
This patch:
- Add the __COHERENT_RAM_START__ and __COHERENT_RAM_END__ symbols.
- Improve how the symbols are found with a regex.
- Add a build option to revert the memory layout output.
Change-Id: I54ec660261431bc98d78acb0f80e3d95bc5397ac
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* changes:
uniphier: make I/O register region configurable
uniphier: make PSCI related base address configurable
uniphier: make counter control base address configurable
uniphier: make UART base address configurable
uniphier: make pinmon base address configurable
uniphier: make NAND controller base address configurable
uniphier: make eMMC controller base address configurable
The offset there is the virtual address space on the bus side (1-9GB for 8GB RAM),
and that emi_mpu_set_region_protection will translate to the physical memory space (0-8GB).
8GB is 33-bit (the memory bus width is 33-bit on this platform),
so 0x23FFFFFFFUL-EMI_PHY_OFFSET = 0x1_FFFF_FFFF.
Change-Id: I7be4759ed7546f7e15a5868b6f08988928c34075
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
DynamIQ based designs have upto 8 CPUs in each cluster. This
patch fixes the device tree node which describes the topology
of the CPU for DynamIQ FVP Model.
Change-Id: I7146bc79029ce38314026d4853e5b6406863725c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Adding support for generating a semi-random number required for
enabling building TF-A with stack protector support.
TF-A for corstone-700 may now be built using ENABLE_STACK_PROTECTOR=all
Change-Id: I03e1be1a8d4e4a822cf286f3b9ad4da4337ca765
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
* changes:
uniphier: extend boot device detection for future SoCs
uniphier: change block_addressing flag to bool
uniphier: change the return value type of .is_usb_boot() to bool
If an SCP firmware is present and able to communicate via SCPI, then use
that to implement CPU and system power state transitions, including CPU
hotplug and system suspend. Otherwise, fall back to the existing CPU
power control implementation.
The last 16 KiB of SRAM A2 are reserved for the SCP firmware, and the
SCPI shared memory is at the very end of this region (and therefore the
end of SRAM A2). BL31 continues to start at the beginning of SRAM A2
(not counting the ARISC exception vector area) and fills up to the
beginning of the SCP firmware.
Because the SCP firmware is not loaded adjacent to the ARISC exception
vector area, the jump instructions used for exception handling cannot be
included in the SCP firmware image, and must be initialized here before
turning on the SCP.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I37b9b9636f94d4125230423726f3ac5e9cdb551c
The function names follow the naming convention used by the existing
ARM SCPI client.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I543bae7d46e206eb405dbedfcf7aeba88a12ca48
The SCP firmware is allocated the last 16KiB of SRAM A2. This includes
the SCPI shared memory area, which must be mapped as MT_DEVICE to
prevent problems with cache coherency between the AP CPUs and the SCP.
For simplicity, map the whole SCP region as MT_DEVICE.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie39eb5ff281b8898a3c1d9748dc08755f528e2f8
The ARISC vector area consists of 0x4000 bytes before the beginning of
usable SRAM. Still, it is technically a part of SRAM A2, so include it
in the memory definition. This avoids the confusing practice of
subtracting from the beginning of the SRAM region when referencing the
ARISC vectors.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iae89e01aeab93560159562692e03e88306e2a1bf
Instead, pass back the error to the calling function. This allows
platform code to fall back to another PSCI implementation if
scpi_wait_ready() or a later SCPI command fails.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ib4411e63c2512857f09ffffe1c405358dddeb4a6
Pad the .rodata section to 16 bytes as ld.lld does not apply the ALIGN
statement on the .data section to the LMA. Fixes boot failure on builds
where the .rodata section happens to not be 16 bytes aligned.
Change-Id: I4e95678f73d8b326c5fc749dc7d0ce84e2d603f5
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Add SMC_GET_GIC_BASE_GICR option to SMC_FC_GET_REG_BASE and
SMC_FC64_GET_REG_BASE calls for returning the base address of the gic
redistributor added in gic version 3.
Bug: 122357256
Change-Id: Ia7c287040656515bab262588163e0c5fc8f13a21
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Some platforms define GICD_BASE instead of PLAT_ARM_GICD_BASE but the
meaning is the same.
Change-Id: I1bb04bb49fdab055b365b1d70a4d48d2058e49df
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Some platforms define BL32_MEM_SIZE instead of TSP_SEC_MEM_SIZE, but
the meaning is the same.
Change-Id: I93d96dca442e653435cae6a165b1955efe2d2b75
Signed-off-by: Arve Hjønnevåg <arve@android.com>
If CC points to clang the linker was set to ld.lld. Copy the diectory
name from CC is it has one.
Change-Id: I50aef5dddee4d2540b12b6d4e68068ad004446f7
Signed-off-by: Arve Hjønnevåg <arve@android.com>
This patch adds information on the PMU configuration registers
and security considerations related to the PMU.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: I36b15060b9830a77d3f47f293c0a6dafa3c581fb
Each memory region slot occupies 16bypte space, so
correct the the offset of config register address.
Change-Id: Ief8f21bb8ada78b5663768ee1e40f9e0eae57165
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
The on-chip SRAM region will be changed in the next SoC. Make it
configurable. Also, split the mmap code into a new helper function
so that it can be re-used for another boot mode.
Change-Id: I89f40432bf852a58ebc9be5d9dec4136b8dc010b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The I/O register region will be changed in the next SoC. Make it
configurable.
Change-Id: Iec0cbd1ef2d0703ebc7c3d3082edd73791bbfec9
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The next SoC will have:
- No boot swap
- SD boot
- No USB boot
Add new fields to handle this.
Change-Id: I772395f2c5dfc612e575b0cbd0657a5fa9611c25
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The register base address will be changed in the next SoC. Make it
configurable.
Change-Id: Ibe07bd9db128b0f7e629916cb6ae21ba7984eca9
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The flag, uniphier_emmc_block_addressing, is boolean logic, so
"bool' is more suitable.
uniphier_emmc_is_over_2gb() is not boolean - it returns 1 / 0
depending on the card density, or a negative value on failure.
Rename it to make it less confusing.
Change-Id: Ia646b1929147b644e0df07c46b54ab80548bc3bd
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The register base will be changed in the next SoC. Make it
configurable.
Change-Id: I4a7cf85fe50e4d71db58a3372a71774e43193bd3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
