Commit Graph

3265 Commits

Author SHA1 Message Date
Michalis Pappas
6a55f6aae9 [PATCH 2/2] qemu: Support MULTI_CONSOLE_API
Add support for the new MULTI_CONSOLE_API

Crash information is now displayed in both the runtime and crash consoles,
if a crash occurs after the runtime console has been enabled

Enable MULTI_CONSOLE_API by default on qemu builds

Fixes ARM-software/tf-issues#561

Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
2018-03-22 10:34:39 +08:00
davidcunado-arm
ff48086b32
Merge pull request #1293 from swarren/issue-551-followup
Don't make build results depend on dependency files
2018-03-21 20:11:19 +00:00
davidcunado-arm
60bb5258f9
Merge pull request #1294 from iwishguo/master
Change PLATFORM_ROOT to TF_PLATFORM_ROOT
2018-03-21 19:20:43 +00:00
davidcunado-arm
6d8db46bec
Merge pull request #1314 from antonio-nino-diaz-arm/an/smccc-header
Rename 'smcc' to 'smccc'
2018-03-21 19:18:29 +00:00
davidcunado-arm
363328063b
Merge pull request #1304 from antonio-nino-diaz-arm/an/fix-copyright
tegra: Use SPDX license identifier
2018-03-21 19:15:40 +00:00
Antonio Nino Diaz
085e80ec11 Rename 'smcc' to 'smccc'
When the source code says 'SMCC' it is talking about the SMC Calling
Convention. The correct acronym is SMCCC. This affects a few definitions
and file names.

Some files have been renamed (smcc.h, smcc_helpers.h and smcc_macros.S)
but the old files have been kept for compatibility, they include the
new ones with an ERROR_DEPRECATED guard.

Change-Id: I78f94052a502436fdd97ca32c0fe86bd58173f2f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-03-21 10:49:27 +00:00
Sandrine Bailleux
0d3feba930 Trusty: Fix sanity check on NS entry point
This patch fixes the sanity check on the non-secure entrypoint value
returned by bl31_plat_get_next_image_ep_info(). This issue has been
reported by Coverity Scan Online:

  CID 264893 (#1 of 1): Dereference null return value (NULL_RETURNS)
  Dereferencing a null pointer ns_ep_info.

Change-Id: Ia0f64d8c8b005f042608f1422ecbd42bc90b2fb4
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-03-21 08:29:31 +01:00
danh-arm
ed8112606c
Fix SDEI link in readme.rst 2018-03-20 17:01:39 +00:00
danh-arm
8f3418b92f
Merge pull request #1316 from davidcunado-arm/dc/version_update
Release v1.5: Update minor version number to 5
2018-03-20 16:50:44 +00:00
danh-arm
cefa8c4390
Merge pull request #1322 from danh-arm/dh/v1.5-readme
Update readme.rst for v1.5 release
2018-03-20 16:50:29 +00:00
danh-arm
1adde117f6
Merge pull request #1326 from JoelHutton/jh/user_guide_updates
Update user guide
2018-03-20 15:19:48 +00:00
Joel Hutton
bf7008a8df Update user guide
Following Out of Box testing for v1.5 release:

    Update host OS version to Ubuntu 16.04
    Clarify configuration files needed for checkpatch
    Add note on using Linaro precompiled binaries

Change-Id: Ia4ae61e01128ddff1a288972ddf84b79370fa52c
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2018-03-20 10:54:44 +00:00
Michalis Pappas
f68d22e879 qemu: Add support for stack canary protection
Allow qemu users to enable stack protection. Since the virt platform
does not provide an RNG, use a basic, timer-based, canary generation,
similarly to FVP.

Increase SRAM size and BL2 size to fit images when stack protection is
enabled.

Notice that stack protection is not enabled by default in qemu.

Fixes ARM-software/tf-issues#568

Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
2018-03-20 14:35:47 +08:00
Michalis Pappas
46e5e035ab Platforms cannot override ENABLE_STACK_PROTECTOR
Include stack_protector's makefile after including platform.mk
to allow platforms override ENABLE_STACK_PROTECTOR

Fixes ARM-software/tf-issues#567

Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
2018-03-20 13:11:12 +08:00
Lin Huang
56bf940730 rockchip/rk3399: save/restore watchdog register correctly
there are two fix for save/restore watchdog register:
1. watchdog plck will shutdown after secure_watchdog_disable(), so need
   to save register before it and restore after secure_watchdog_enable().
2. need write 0x76 to cnt_restart to keep watchdog alive when restore
   watchdog register.

Change-Id: I1f6fbceae22186e3b72a87df6332a110adf37479
Signed-off-by: Lin Huang <hl@rock-chips.com>
2018-03-20 09:42:27 +08:00
Dan Handley
5b0b72760b Update readme.rst for v1.5 release
Change-Id: Id9bd0c20a5af4f41269a51a675018dcc59e93f6c
Signed-off-by: Dan Handley <dan.handley@arm.com>
2018-03-19 18:06:03 +00:00
Wang Feng
39b21d19a0 FVP: change the method for translating MPIDR values to a linear indices
x3 will be assigned by the folloing instructions.
So the first instruction is not needed any more.

old method:
  (ClusterId * FVP_MAX_CPUS_PER_CLUSTER)
+ (CPUId * FVP_MAX_PE_PER_CPU)
+ ThreadId

it should be
  (ClusterId * FVP_MAX_CPUS_PER_CLUSTER) * FVP_MAX_PE_PER_CPU
+ (CPUId * FVP_MAX_PE_PER_CPU)
+ ThreadId

which can be simplified as:
(ClusterId * FVP_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_MAX_PE_PER_CPU + ThreadId

Signed-off-by: Wang Feng <feng_feng.wang@spreadtrum.com>
2018-03-17 14:51:58 +08:00
David Cunado
4a577f9628 Release v1.5: Update minor version number to 5
Change-Id: Ib215150272acc2ecec43f9b69624ebbbd5d7492d
Signed-off-by: David Cunado <david.cunado@arm.com>
2018-03-16 21:04:51 +00:00
davidcunado-arm
fb45044bc5
Merge pull request #1312 from davidcunado-arm/dc/update_docs
Docs: Update various for v1.5 release
2018-03-15 20:41:16 +00:00
Jolly Shah
37e1a68e58 zynqmp: pm: Minor corrections for MISRA compliance
Various changes to comply with MISRA static analysis rules

Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:28:29 -07:00
Rajan Vaja
cc974c52c2 zynqmp: pm_service: Support multiple SDIO modes
Existing database allows to set only single mode for SDIO.
SDIO can have different groups (8 bit, 4 bit and 1 bit).
As there is only single SDIO group in each pin, it is not
 possible to use different mode groups for SDIO.

Extend database in generic way to allow multiuple function
groups in single pin. Add different SDIO groups to pins and
create separate functions for each modes.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
2018-03-15 10:24:14 -07:00
Rajan Vaja
f134200f1a zynqmp: pm: Support ATF PM version check
Add SMC call to query ATF PM version. This version
can be used by Linux to match with expected version.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
2018-03-15 10:24:09 -07:00
Jolly Shah
96d6986566 zynqmp: pm: Update API version to 1.0
With new EEMI APIs addition, version is updated to 1.0

Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:24:04 -07:00
Jolly Shah
3077f8d96a zynqmp: Use DDR memory when DEBUG is enabled
Define default DDR location to which ATF has to compiled
if DEBUG option is enabled. This is required now, as the ATF cant fit
in OCM with DEBUG option enabled. The default value is 0x1000 and can be
used till 0x7ffff. User can still override as per wish/requirement
using current commandline options.

Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:24:00 -07:00
Rajan Vaja
bd99265b06 zynqmp: pm: Add APIs for pin control queries
Add pin control APIs which driver can use to query
pin information from firmware. Using these APIs,
driver do not need to maintain hard-coded pin database.

Major changes in patch are:
- Add pin database with pins, functions and function groups
  information
- Implement APIs for pin information queries
- Update pin control APIs for get/set functions to use new
  pin control database. Remove pin database which was added
  earlier.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:23:54 -07:00
Rajan Vaja
63eb7a367d zynqmp: pm: Add IOCTLs for global storage access
Add IOCTLs to read/write global general storage and
persistent global general storage registers access.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:23:49 -07:00
Rajan Vaja
1a3f02b5a3 zynqmp: pm: Implement clock APIs
- Add clock entries and information to clock database.
- Implement APIs to provide clock topology and other
  information to caller.
- Implement APIs to control clocks and PLLs.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:23:46 -07:00
Rajan Vaja
caae497dfc zynqmp: pm: Add clock control EEMI API and ioctl functions
These are empty functions with no logic right now. Code
will be added in subsequent commits.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:23:41 -07:00
Rajan Vaja
1818c02925 zynqmp: pm: Implement IOCTL APIs for device control
Implement ioctl APIs which uses MMIO operations
to configure devices. Below IOCTLs are supported
in this patch:
  * Set tap delay bypass
  * Set SGMII mode
  * SD reset
  * Set SD/MMC tap delay

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:23:36 -07:00
Rajan Vaja
f76918a806 zynqmp: pm: Implement IOCTL APIs for remoteproc
Implement ioctl APIs which uses MMIO operations
to control RPU operations. Below IOCTLs are supported
in this patch:
  * Get RPU operation mode
  * Set RPU operation mode
  * Configure RPU boot address (OCM/TCM)
  * Configure TCM combined mode

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:23:31 -07:00
Rajan Vaja
d0e2c51ae3 zynqmp: pm: Implement pin control APIs for configurations
Implement pin control APIs which uses MMIO operations
to set/get values of configuration parameters.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:23:27 -07:00
Rajan Vaja
e52e10add2 zynqmp: pm: Implement pin control APIs for get/set functions
Implement pin control APIs which uses MMIO operations
to set/get functions for the given pin.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:23:22 -07:00
Rajan Vaja
849ba7f730 zynqmp: pm: Add wrappers for Pin control APIs
Add wrappers for pin control APIs. Actual implementation of
these APIs would be done in subsequent changes.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:23:17 -07:00
Rajan Vaja
f61262ac62 zynqmp: Add new function and node IDs
Add new function and node IDs supported by PMUFW in
function list and node list respectively.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
2018-03-15 10:23:12 -07:00
David Cunado
855ac025f1 Update model support in User Guide
The CI has been updated to run tests against the AEMv8-A RevC
model, FVP_Base_RevC-2xAEMv8A, which is available from the Fast
Model releases on Connected Community [1].

Additionally, the CI now also includes the Cortex-A55x4, Cortex-A75x4
and Cortex-A55x4-A75x4 Base models.

[1] https://developer.arm.com/products/system-design/fixed-virtual-platforms

Change-Id: I57806f3b2a8121211490a7aa0089dcae566d8635
Signed-off-by: David Cunado <david.cunado@arm.com>
2018-03-15 17:00:34 +00:00
David Cunado
230326fa56 Update change-log.rst for v1.5
Updated change-log.rst with summary of changes since
release v1.4.

Change-Id: I56b5a30d13a5a7099942535cbaeff0e2a5c5804e
Signed-off-by: David Cunado <david.cunado@arm.com>
2018-03-15 17:00:34 +00:00
Dan Handley
4def07d535 Update Arm TF references to TF-A
Update Arm Trusted Firmware references in the upstream documents to
Trusted Firmware-A (TF-A). This is for consistency with and
disambiguation from Trusted Firmware-M (TF-M).

Also update other Arm trademarks, e.g. ARM->Arm, ARMv8->Armv8-A.

Change-Id: I8bb0e18af29c6744eeea2dc6c08f2c10b20ede22
Signed-off-by: Dan Handley <dan.handley@arm.com>
Signed-off-by: David Cunado <david.cunado@arm.com>
2018-03-15 17:00:34 +00:00
davidcunado-arm
c3e34a9e01
Merge pull request #1308 from soby-mathew/sm/doc_dyn_cfg
Docs: Update design guide for dynamic config
2018-03-15 15:27:08 +00:00
davidcunado-arm
1d060675d2
Merge pull request #1310 from JoelHutton/jh/aarch32_mem_protect_fix
FVP AArch32: Fix flash access in BL32 for mem_protect
2018-03-15 15:24:37 +00:00
Jonathan Wright
5ea2827734 stdlib: remove comparison with EOF macro to comply with MISRA
Ensures compliance with MISRA C-2012 Rule 22.7

Change-Id: Ifbe0926a24ba0dca18174e1aa87313a63bba50fb
Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
2018-03-15 13:32:54 +00:00
Joel Hutton
950c69563f FVP AArch32: Fix flash access in BL32 for mem_protect
The FVP platform port for SP_MIN (BL32) didn't map the flash memory
in BL32 for stroring the mem_protect enable state information leading
to synchronous exception. The patch fixes it by adding the region to
the BL32 mmap tables.

Change-Id: I37eec83c3e1ea43d1b5504d3683eebc32a57eadf
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2018-03-15 11:45:37 +00:00
davidcunado-arm
6dd74c5b65
Merge pull request #1305 from dp-arm/dp/smccc
Implement support for v1.2 of firmware interfaces spec (ARM DEN 0070A)
2018-03-14 14:24:25 +00:00
Dimitris Papastamos
a205a56ea8 Fixup SMCCC_ARCH_FEATURES semantics
When querying `SMCCC_ARCH_WORKAROUND_1` through `SMCCC_ARCH_FEATURES`,
return either:
  * -1 to indicate the PE on which `SMCCC_ARCH_FEATURES` is called
    requires firmware mitigation for CVE-2017-5715 but the mitigation
    is not compiled in.
  * 0 to indicate that firmware mitigation is required, or
  * 1 to indicate that no firmware mitigation is required.

This patch complies with v1.2 of the firmware interfaces
specification (ARM DEN 0070A).

Change-Id: Ibc32d6620efdac6c340758ec502d95554a55f02a
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-14 11:19:53 +00:00
Dimitris Papastamos
3991a6a49f Use PFR0 to identify need for mitigation of CVE-2017-5715
If the CSV2 field reads as 1 then branch targets trained in one
context cannot affect speculative execution in a different context.
In that case skip the workaround on Cortex A72 and A73.

Change-Id: Ide24fb6efc77c548e4296295adc38dca87d042ee
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-14 11:15:44 +00:00
Soby Mathew
b2a68f88c1 Docs: Update design guide for dynamic config
This patch updates the `firmware-design.rst` document for
changes in ARM-TF for supporting dynamic configuration features
as presented in `Secure Firmware BoF SFO'17`[1].

The patch also updates the user-guide for 2 build options for FVP
pertaining to dynamic config.

[1] https://www.slideshare.net/linaroorg/bof-device-tree-and-secure-firmware-bof-sfo17310

Change-Id: Ic099cf41e7f1a98718c39854e6286d884011d445
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-03-13 19:12:27 +00:00
Michael Brandl
4368ae07ba plat/hikey: boot memory layout to dedicated file
Boot memory layout is specific for a platform, but should not be
mixed up with other platform specific attributes. A separate file is
much cleaner and better to compare with other platforms. Take a look
at plat/poplar where it is done the same way.

Moved hikey_def.h to system include folder and moved includes from
hikey_def.h to more general platform_def.h.

Signed-off-by: Michael Brandl <git@fineon.pw>
2018-03-12 13:19:00 +01:00
davidcunado-arm
16b05e94a2
Merge pull request #1303 from soby-mathew/sm/fix_juno_fwu
Juno: Fixes for firmware update
2018-03-08 11:33:41 +00:00
Antonio Nino Diaz
41376c3a4a tegra: Use SPDX license identifier
Change-Id: I770b2db68c8d115d10067bb557e32b5e269c94a5
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-03-08 10:57:43 +00:00
davidcunado-arm
bf35944bf6
Merge pull request #1277 from hzhuang1/testing/bl2_el3_v0.6
hikey: migrate to BL2_EL3
2018-03-08 10:39:52 +00:00
Soby Mathew
7b56928a12 Juno: Change the Firmware update detect mechanism
Previously, Juno used to depend on the SSC_GPRETN register to inform
about the reset syndrome. This method was removed when SCP migrated
to the SDS framework. But even the SDS framework doesn't report the
reset syndrome correctly and hence Juno failed to enter Firmware
update mode if BL2 authentication failed.

In addition to that, the error code populated in V2M_SYS_NVFLAGS register
does not seem to be retained any more on Juno across resets. This could
be down to the motherboard firmware not doing the necessary to preserve
the value.

Hence this patch modifies the Juno platform to use the same mechanism to
trigger firmware update as FVP which is to corrupt the FIP TOC on
authentication failure. The implementation in `fvp_err.c` is made common
for ARM platforms and is moved to the new `arm_err.c` file in
plat/arm/common folder. The BL1 and BL2 mmap table entries for Juno
are modified to allow write to the Flash memory address.

Change-Id: Ica7d49a3e8a46a90efd4cf340f19fda3b549e945
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-03-08 09:44:05 +00:00