Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I89c3ab2ed85ab941d8b38ced48474feb4aaa8b7e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I058f793e4024fa7291e432f5be374a77faf16f36
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location for the coreboot memory console.
This removes the base member from the coreboot specific data structure,
but keeps the struct console_cbmc_t and its size member.
Change-Id: I7f1dffd41392ba3fe5c07090aea761a42313fb5b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I347849424782333149e5912a25cc0ab9d277a201
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I9f8b55414ab7965e431e3e86d182eabd511f32a4
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I7a23327394d142af4b293ea7ccd90b843c54587c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I07a07677153d3671ced776671e4f107824d3df16
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
*All* UART drivers in TF-A are storing their base address as a uintptr_t
pointer in the first location of the UART specific driver data.
Since the base address is a pretty natural and generic data item, we
should integrate this into the generic console_t structure.
That will not only allow to remove a lot of seemingly UART specific data
structures, but also enables to simplify runtime choices between different
UARTs, since they can share the same pointer.
This patch just adds the new member, the existing data structures will
be handled on a per-UART base in follow-up patches.
Change-Id: I59ce49471ccc8f3b870f2cfd8a72ebfd0cb14d12
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
There are chances a denial-of-service attack, if an attacker
removes the SPE firmware from the system. The console driver
would end up waiting for the firmware to respond indefinitely.
The console driver must detect such scenarios and uninit the
interface as a result.
This patch adds a timeout to the interaction with the SPE
firmware and uninits the interface if it times out.
Change-Id: I06f27a858baed25711d41105b4110865f1a01727
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".
This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".
Original change by: kalyani chidambaram <kalyanic@nvidia.com>
Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Code complexity is a good indication of maintainability versus
testability of a piece of software.
ISO26262 introduces the following thresholds:
complexity < 10 is accepted
10 <= complexity < 20 has to be justified
complexity >= 20 cannot be accepted
Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.
This patch removes redundant conditionals from 'ipc_send_req_atomic'
handler to reduce the McCabe Cyclomatic Complexity for this function
Change-Id: I20fef79a771301e1c824aea72a45ff83f97591d5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZDRAM memory as the previous bootloader
relies on BL31 to do so.
Change-Id: Ibb864901e43aca5bf55d8c79e918b598c12e8a28
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Code complexity is a good indication of maintainability versus
testability of a piece of software.
ISO26262 introduces the following thresholds:
complexity < 10 is accepted
10 <= complexity < 20 has to be justified
complexity >= 20 cannot be accepted
Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.
This patch removes redundant conditionals from 'bl31_early_platform_setup'
handler to reduce the McCabe Cyclomatic Complexity for this function.
Change-Id: Ifb628e33269b388f9323639cd97db761a7e049c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch sets the "secure" bit to mark the PMC hardware block
as accessible only from the secure world. This setting must be
programmed during cold boot and System Resume.
The sc7entry-fw, running on the COP, needs access to the PMC block
to enter System Suspend state, so "unlock" the PMC block before
passing control to the COP.
Change-Id: I00e39a49ae6b9f8c8eafe0cf7ff63fe6a67fdccf
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
This patch modifies the delay timer driver to switch to the ARM
secure physical timer instead of using Tegra's on-chip uS timer.
The secure timer is not accessible to the NS world and so eliminates
an important attack vector, where the Tegra timer source gets switched
off from the NS world leading to a DoS attack for the trusted world.
This timer is shared with the S-EL1 layer for now, but later patches
will mark it as exclusive to the EL3 exception mode.
Change-Id: I2c00f8cb4c48b25578971c626c314603906ad7cc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch moves the MHZ_TICKS_PER_SEC macro to utils_def.h
for other platforms to use.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I6c4dc733f548d73cfdb3515ec9ad89a9efaf4407
This patch locks most of the stream id security config registers as
per HW guidance.
This patch keeps the stream id configs unlocked for the following
clients, to allow some platforms to still function, until they make
the transition to the latest guidance.
- ISPRA
- ISPFALR
- ISPFALW
- ISPWA
- ISPWA1
- ISPWB
- XUSB_DEVR
- XUSB_DEVW
- XUSB_HOSTR
- XUSB_HOSTW
- VIW
- VIFALR
- VIFALW
Change-Id: I66192b228a0a237035938f498babc0325764d5df
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
The PMC hardware block resume handler was called for Tegra210
platforms, only if the sc7entry-fw was present on the device.
This would cause problems for devices that do not support this
firmware.
This patch fixes this logic and resumes the PMC block even if
the sc7entry-fw is not present on the device.
Change-Id: I6f0eb7878126f624ea98392f583ed45a231d27db
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
This patch adds the macro to enable legacy FIQ handling to the common
Tegra makefile. The default value of this macro is '0'. Platforms that
need this support should enable it from their makefiles.
This patch also helps fix violation of Rule 20.9.
Rule 20.9 "All identifiers used in the controlling expression of #if
of #elif preprocessing directives shall be #define'd before
evaluation"
Change-Id: I4f0c9917c044b5b1967fb5e79542cd3bf6e91f18
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable
non-cacheable streaming enhancement. Platforms can set this bit only
if their memory system meets the requirement that cache line fill
requests from the Cortex-A57 processor are atomic.
This patch adds support to enable higher performance non-cacheable load
forwarding for such platforms. Platforms must enable this support by
setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their
makefiles. This flag is disabled by default.
Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Removed duplicate error code present for SMCCC and used
proper error code for "SMCCC_ARCH_WORKAROUND_2" call.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I76fc7c88095f78a7e2c3d205838f8eaf3132ed5c
Fix mailbox driver incompatible cast bug and control flow issue that
was flagged by Coverity Scan.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f34e98d24e40139d31cf7d5b9b973cd2d981065
Use CREATE_SEQ helper macro to create sequence of valid chip counts
instead of manually creating the sequence. This allows a scalable
approach to increase the valid chip count sequence in the future.
Change-Id: I5ca7a00460325c156b9e9e52b2bf656a2e43f82d
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Add `CREATE_SEQ` function to generate sequence of numbers starting from
1 to allow easy comparison of a user defined macro with non-zero
positive numbers.
Change-Id: Ibcb336a223d958154b1007d08c428fbaf1e48664
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
This patch allows to use DDR address in memory node because on FPGA we
typically use DDR instead of shared RAM.
This patch also modifies the kernel arguments to allow the rootfs to be
mounted from a direct mapping of the QSPI NOR flash using the physmap
driver in the kernel. This allows to support CRAMFS XIP.
Change-Id: I4e2bc6a1f48449c7f60e00f5f1a698df8cb2ba89
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Fixes for the following MISRA violations:
- Missing explicit parentheses on sub-expression
- An identifier or macro name beginning with an
underscore, shall not be declared
- Type mismatch in BL1 SMC handlers and tspd_main.c
Change-Id: I7a92abf260da95acb0846b27c2997b59b059efc4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
* changes:
Fix boot failures on some builds linked with ld.lld.
trusty: generic-arm64-smcall: Support gicr address
trusty: Allow gic base to be specified with GICD_BASE
trusty: Allow getting trusty memsize from BL32_MEM_SIZE instead of TSP_SEC_MEM_SIZE
Fix clang build if CC is not in the path.
When TF-A is built with RESET_TO_BL31=1 option, BL31 is the
first image to be run and should have all the memory allocated
to it except for the memory reserved for Shared RAM at the start
of Trusted SRAM.
This patch fixes FVP BL31 load address and its image size for
RESET_TO_BL31=1 option. BL31 startup address should be set to
0x400_1000 and its maximum image size to the size of Trusted SRAM
minus the first 4KB of shared memory.
Loading BL31 at 0x0402_0000 as it is currently stated in
'\docs\plat\arm\fvp\index.rst' causes EL3 exception when the
image size gets increased (i.e. building with LOG_LEVEL=50)
but doesn't exceed 0x3B000 not causing build error.
Change-Id: Ie450baaf247f1577112f8d143b24e76c39d33e91
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
The TBBR implementation extracts hashes from certificates and stores
them in static buffers. TF-A supports 3 variants of SHA right now:
SHA-256, SHA-384 and SHA-512. When support for SHA-512 was added in
commit 9a3088a5f5 ("tbbr: Add build flag
HASH_ALG to let the user to select the SHA"), the hash buffers got
unconditionally increased from 51 to 83 bytes each. We can reduce that
space if we're using SHA-256 or SHA-384.
This saves some BSS space in both BL1 and BL2:
- BL1 with SHA-256: saving 168 bytes.
- BL1 with SHA-384: saving 80 bytes.
- BL2 with SHA-256: saving 384 bytes.
- BL2 with SHA-384: saving 192 bytes.
Change-Id: I0d02e5dc5f0162e82339c768609c9766cfe7e2bd
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
The TBBR implementation extracts public keys from certificates and
stores them in static buffers. DER-encoded ECDSA keys are only 91 bytes
each but were each allocated 294 bytes instead. Reducing the size of
these buffers saves 609 bytes of BSS in BL2 (294 - 91 = 203 bytes for
each of the 3 key buffers in use).
Also add a comment claryfing that key buffers are tailored on RSA key
sizes when both ECDSA and RSA keys are used.
Change-Id: Iad332856e7af1f9814418d012fba3e1e9399f72a
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
