Commit Graph

2823 Commits

Author SHA1 Message Date
Dimitris Papastamos
b6eb39327c AMU: Add hooks to save/restore AMU context
On some systems, the AMU counters might reset to 0 when a CPU
powerdown happens.  This behaviour conflicts with the intended
use-case of AMU as lower ELs are only expected to see non-decreasing
counter values.

Change-Id: If25519965d4e6e47e09225d0e732947986cbb5ec
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11 14:36:45 +00:00
Dimitris Papastamos
0767d50e69 AMU: Add configuration helpers for aarch64
Add some AMU helper functions to allow configuring, reading and
writing of the Group 0 and Group 1 counters.  Documentation for these
helpers will come in a separate patch.

Change-Id: I656e070d2dae830c22414f694aa655341d4e2c40
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11 12:27:29 +00:00
Dimitris Papastamos
59902b7c4c AMU: Add plat interface to select which group 1 counters to enable
A new platform macro `PLAT_AMU_GROUP1_COUNTERS_MASK` controls which
group 1 counters should be enabled. The maximum number of group 1
counters supported by AMUv1 is 16 so the mask can be at most 0xffff.
If the platform does not define this mask, no group 1 counters are
enabled.

A related platform macro `PLAT_AMU_GROUP1_NR_COUNTERS` is used by
generic code to allocate an array to save and restore the counters on
CPU suspend.

Change-Id: I6d135badf4846292de931a43bb563077f42bb47b
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11 12:27:27 +00:00
Dimitris Papastamos
7593252cee Add PubSub events for CPU powerdown/powerup
The suspend hook is published at the start of a CPU powerdown
operation.  The resume hook is published at the end of a CPU powerup
operation.

Change-Id: I50c05e2dde0d33834095ac41b4fcea4c161bb434
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11 10:33:41 +00:00
davidcunado-arm
08e06be819
Merge pull request #1176 from wjliang/zynqmp-ipi-mb-svc
plat: xilinx: Add ZynqMP IPI mailbox service [v4]
2018-01-10 14:57:22 +00:00
davidcunado-arm
210d8d8b8a
Merge pull request #1208 from masahir0y/build
Build: trivial fixes
2018-01-10 01:10:51 +00:00
davidcunado-arm
8d356425e5
Merge pull request #1207 from hzhuang1/isp_clk
hikey960: set isp clks as unsecure mode
2018-01-10 00:21:25 +00:00
davidcunado-arm
c14d3dcd47
Merge pull request #1167 from Leo-Yan/hikey-fix-alignment
Set alignment size to 512B for Hikey/Hikey960
2018-01-09 08:58:41 +00:00
Wendy Liang
ebc05162ae zynqmp: pm_service: use zynqmp_ipi APIs
Use zynqmp_ipi APIs to access IPI registers in pm_service.
As the zynqmp_ipi APIs doesn't cover IPI buffers, the pm_ipi
in pm_service will still directly access the IPI buffers.

Signed-off-by: Wendy Liang <jliang@xilinx.com>
2018-01-08 16:03:09 -08:00
Wendy Liang
e8ffe79d06 Add Xilinx ZynqMP IPI mailbox service
Add IPI mailbox service to manage Xilinx ZynqMP IPI(Inter Processors
Interrupt) access.

Signed-off-by: Wendy Liang <jliang@xilinx.com>
2018-01-08 16:03:09 -08:00
Wendy Liang
dc1dfe831f Introduce ZynqMP IPI implementation
Previously, ZynqMP IPI in ATF is only for ZynqMP PM,
This patch is to have a ZynqMP IPI implementation to handle
both ZynqMP PM IPI requirement and IPI mailbox service requirement
which will be introduced next.

We control IPI agents registers access but not IPI buffers access in
this implementation. Each IPI mailbox user will directly access the
IPI buffers.

Signed-off-by: Wendy Liang <jliang@xilinx.com>
2018-01-08 16:03:09 -08:00
davidcunado-arm
77796fb7c5
Merge pull request #1202 from antonio-nino-diaz-arm/an/spm-secondary-cores
SPM: Allow secondary CPUs to use the Secure Partition
2018-01-08 22:59:37 +00:00
Antonio Nino Diaz
a43c85db2d SPM: Allow secondary CPUs to use the Secure Partition
The Secure Partition should be able to be used from any CPU, not just
the lead one. This patch point the secure contexts of all secondary
CPUs to the same one used by the lead CPU for the Secure Partition. This
way, they can also use it.

In order to prevent more than one CPU from using the Secure Partition at
the same time, a lock has been added.

Change-Id: Ica76373127c3626498b06c558a4874ce72201ff7
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-01-08 09:59:33 +00:00
Antonio Nino Diaz
26bd5f8245 SPM: Move initialization flag to context struct
Whether a Secure Partition is being initialized or not is something
related to that specific partition, so it should be saved with the
rest of the information related to it.

Change-Id: Ie8a780f70df83fb03ef9c01ba37960208d9b5319
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-01-08 09:58:15 +00:00
davidcunado-arm
6ef96ab4fd
Merge pull request #1204 from davidcunado-arm/rv/fip_tool
Add padding at the end of the last entry
2018-01-03 23:48:51 +00:00
davidcunado-arm
8618856733
Merge pull request #1206 from davidcunado-arm/dc/update_userguide
Update dependencies for ARM TF
2018-01-03 21:13:43 +00:00
Jett Zhou
4069fb5f39 docs: Update the ToC end marker description in the document
Change-Id: I2e29a63f08aed3b8ea0bb10170a3d55b8d033e62
Signed-off-by: Jett Zhou <jett.zhou@arm.com>
Signed-off-by: David Cunado <david.cunado@arm.com>
2018-01-03 20:51:43 +00:00
Roberto Vargas
880b9e8b4c Add padding at the end of the last entry
This patch adds padding bytes at the end of the last image in the
fip to be able to transfer by DMA the last image.

Change-Id: I8c6f07dee389cb3d1dc919936d9d52841d7e5723
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Signed-off-by: David Cunado <david.cunado@arm.com>
2018-01-03 20:51:43 +00:00
davidcunado-arm
34c2b9c2f1
Merge pull request #1212 from dp-arm/dp/tsp_dram
Move TSP to TZC secured DRAM
2018-01-03 11:20:56 +00:00
Dimitris Papastamos
66db10ca41 Move TSP to TZC secured DRAM
To allow BL31 to grow in SRAM, move TSP in TZC secured DRAM
by default.

Increase the BL31 max limit by one page.

Change-Id: Idd3479be02f0f9bafac2f275376d7db0c2015431
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-03 10:21:26 +00:00
davidcunado-arm
9a2a38a201
Merge pull request #1203 from masahir0y/uniphier
uniphier: a bundle of fixes
2017-12-24 19:52:17 +00:00
Masahiro Yamada
87ebd20d4b Build: specify check_* targets as .PHONY
check_* targets just check necessary command line argument, not
build any images.  They should be specified as .PHONY.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-24 22:45:53 +09:00
davidcunado-arm
ac4626dc48
Merge pull request #1201 from jeenu-arm/sdei-plat-events
ARM platforms: Allow platforms to define SDEI events
2017-12-24 10:58:53 +00:00
Masahiro Yamada
1e0c078425 Build: update comment lines for macros
Commit 8f0617ef9e ("Apply TBBR naming convention to the fip_create
options") changed fiptool command options.  We often forget to update
documentation.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-23 23:56:18 +09:00
David Cunado
fa05efb3d5 Update dependencies for ARM TF
ARM TF has been tested as part of its CI system with the following
dependencies updated:

- Linaro binaries:    17.04 --> 17.10
- mbed TLS library:   2.4.2 --> 2.6.0

The version of AEM, Cortex-A and Foundation models that ARM TF is
tested on has also been updated:

- v11.1 build 11.1:22 --> v11.2 build 11.2:33
- v8.9 build 0.8:8805 --> v9.0 build 0.8:9005

This patch updates the user guide documentation to reflect these
changes to the dependencies.

Additionally, links to Linaro resources have been updated.

Change-Id: I9ea5cb76e7443c9dbb0c9525069f450a02f59e58
Signed-off-by: David Cunado <david.cunado@arm.com>
2017-12-21 09:43:49 +00:00
davidcunado-arm
3c95ea01a2
Merge pull request #1198 from antonio-nino-diaz-arm/an/spm-doc
Add Secure Partition Manager (SPM) design document
2017-12-20 10:59:15 +00:00
Masahiro Yamada
9d32b55ccb uniphier: fix alignment of build log
The build log should be indented with two spaces for correct alignment.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-20 12:33:01 +09:00
Masahiro Yamada
fe458325d0 uniphier: fix base address of IO block buffer
The current IO block buffer overlaps with BL2 image location.
So, BL2 may corrupt itself.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-20 12:33:01 +09:00
Masahiro Yamada
58b6fccffe doc: uniphier: reformat reStructuredText manually
Commit 6f62574767 ("Convert documentation to reStructuredText")
automatically converted all documents by a tool.  I see some parts
were converted in an ugly way (or, at least, it is not my intention).
Also, the footnote is apparently broken.

I checked this document by my eyes, and reformated it so that it looks
nicer both in plain text and reST form.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-20 12:33:01 +09:00
davidcunado-arm
1e49e906b1
Merge pull request #1196 from antonio-nino-diaz-arm/an/zero-pad
Add support to left-pad with zeroes in tf_printf
2017-12-19 21:51:08 +00:00
davidcunado-arm
9f36f4c4e7
Merge pull request #1195 from davidcunado-arm/dc/fix_pie
Disable PIE compilation option
2017-12-19 20:41:53 +00:00
davidcunado-arm
dced20e17b
Merge pull request #1194 from robertovargas-arm/io-fix
io: block: fix block_read/write may read/write overlap buffer
2017-12-19 17:39:20 +00:00
davidcunado-arm
468c55770b
Merge pull request #1192 from sandrine-bailleux-arm/sb/fix-mm-communicate
SPM: Fix MM_COMMUNICATE_AARCH32/64 parameters
2017-12-19 15:58:32 +00:00
Jeenu Viswambharan
7bdf0c1ffa ARM platforms: Allow platforms to define SDEI events
With this patch, ARM platforms are expected to define the macros
PLAT_ARM_SDEI_PRIVATE_EVENTS and PLAT_ARM_SDEI_SHARED_EVENTS as a list
of private and shared events, respectively. This allows for individual
platforms to define their own events.

Change-Id: I66851fdcbff83fd9568c2777ade9eb12df284b49
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-12-19 08:55:12 +00:00
davidcunado-arm
725912d82f
Merge pull request #1190 from vchong/poplar_hisi_review2
poplar: Add BL32 (OP-TEE) support and misc updates
2017-12-18 14:28:46 +00:00
Haojian Zhuang
f7ff1084ec hikey960: set isp clks as unsecure mode
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-12-18 09:45:37 +08:00
Antonio Nino Diaz
84816dcd7c Add support to left-pad with zeroes in tf_printf
Add support to formats %i, %d, %p, %x and %u for left-padding numbers
with zeroes (e.g. `%08x`).

Change-Id: Ifd4795a82a8d83da2c00b44b9e482a2d9be797e3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-12-15 15:03:48 +00:00
Antonio Nino Diaz
100ac09097 Add Secure Partition Manager (SPM) design document
This patch adds documentation that describes the design of the Secure
Partition Manager and the specific choices in their current
implementation.

The document "SPM User Guide" has been integrated into the design
document.

Change-Id: I0a4f21a2af631c8aa6c739d97a5b634f3cb39991
Co-authored-by: Achin Gupta <achin.gupta@arm.com>
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-12-15 11:47:22 +00:00
david cunado
f7ec31db2d Disable PIE compilation option
ARM TF does not work correctly if built with a version of gcc
that is configured to use PIE by default (e.g. Debian Stretch).

This patch identifies when such a version of gcc is being used
(by searching for --enable-default-pie) and adds -fno-PIE option
to TF_CFLAGS.

fixes arm-software/tf-issues#519

Change-Id: I2322122c49841746d35d152694e14f6f73beb0fd
Signed-off-by: David Cunado <david.cunado@arm.com>
Co-Authored-by: Evan Lloyd <evan.lloyd@arm.com>
Tested-by: Steve Capper <steve.capper@arm.com>
Tested-by: Alexei Fedorov <alexei.fedorov@arm.com>
2017-12-14 23:36:15 +00:00
davidcunado-arm
842c00eb44
Merge pull request #1104 from nmenon/dtb_build-v2
Makefile: Add ability to build dtb (v2)
2017-12-14 22:11:06 +00:00
Roberto Vargas
e19e40af97 io: block: fix block_read/write may read/write overlap buffer
The block operations were trying to optimize the number of memory
copies, and it tried to use directly the buffer supplied by the user
to them. This was a mistake because it created too many corner cases:

	1- It was possible to generate unaligned
	   operations to unaligned buffers. Drivers that were using
	   DMA transfer failed in that case.

	2- It was possible to generate read operations
	   with sizes that weren't a multiple of the block size. Some
	   low level drivers assumed that condition and they calculated
	   the number of blocks dividing the number of bytes by the
	   size of the block, without considering the remaining bytes.

	3- The block_* operations didn't control the
	   number of bytes actually copied to memory, because the
	   low level drivers were writing directly to the user buffer.

This patch rewrite block_read and block_write to use always the device
buffer, which the platform ensures that has the correct aligment and
the correct size.

Change-Id: I5e479bb7bc137e6ec205a8573eb250acd5f40420
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2017-12-13 09:13:37 +00:00
Sandrine Bailleux
4d2787cead SPM: Fix MM_COMMUNICATE_AARCH32/64 parameters
This partially reverts commit d6b532b50f, keeping only the fixes to
the assertions. The changes related to the order of arguments passed
to the secure partition were not correct and violated the
specification of the SP_EVENT_COMPLETE SMC.

This patch also improves the MM_COMMUNICATE argument validation.  The
cookie argument, as it comes from normal world, can't be trusted and thus
needs to always be validated at run time rather than using an assertion.

Also validate the communication buffer address and return
INVALID_PARAMETER if it is zero, as per the MM specification.

Fix a few typos in comments and use the "secure partition" terminology
rather than "secure payload".

Change-Id: Ice6b7b5494b729dd44611f9a93d362c55ab244f7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2017-12-12 15:05:21 +00:00
Victor Chong
f336774b45 poplar: Add BL32 (OP-TEE) support
Signed-off-by: Victor Chong <victor.chong@linaro.org>
2017-12-12 13:01:09 +09:00
Jiancheng Xue
d45a1c303e Poplar: Initialize security properties of IP blocks.
The security properties of some IP blocks are configured to secure mode
after reset. This means these IP blocks can only be accessed by cpus
in secure state by default. These should be configured correclty as needed.

Signed-off-by: y00241285 <yyangwei.yangwei@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
2017-12-12 13:01:09 +09:00
Victor Chong
94725a26d8 poplar: Increase FIP_SIZE
This is currently the maximum allowed without affecting bootup.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
2017-12-12 13:01:09 +09:00
Victor Chong
5a3ec61f53 poplar: Rename PLAT_ARM_NS_IMAGE_OFFSET
to PLAT_POPLAR_NS_IMAGE_OFFSET

Signed-off-by: Victor Chong <victor.chong@linaro.org>
2017-12-12 13:01:09 +09:00
Victor Chong
78896ac36e poplar: Fix GPIO_MAX
Per
https://github.com/sdrobertw/Poplar/blob/master/HardwareDocs/Processor_Datasheet_v2XX.pdf
there are 13 groups of GPIO controllers, not 12.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
2017-12-12 13:01:09 +09:00
davidcunado-arm
211d307c6b
Merge pull request #1178 from davidcunado-arm/dc/enable_sve
Enable SVE for Non-secure world
2017-12-11 12:29:47 +00:00
davidcunado-arm
83df7ce38d
Merge pull request #1187 from antonio-nino-diaz-arm/an/spm-xlat-dram
SPM: Move S-EL1/S-EL0 xlat tables to TZC DRAM
2017-12-10 14:01:37 +00:00
davidcunado-arm
9f0ee04f5d
Merge pull request #1184 from antonio-nino-diaz-arm/an/bl31-in-dram
fvp: Disable SYSTEM_SUSPEND when ARM_BL31_IN_DRAM
2017-12-09 23:10:24 +00:00