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This patch adds links to the Cortex-A53 and Cortex-A57 MPCores Software Developers Errata Notice documents in the ARM CPU Specific Build Macros document. Change-Id: I0aa26d7f373026097ed012a02bc61ee2c5b9d6fc
119 lines
5.7 KiB
Markdown
119 lines
5.7 KiB
Markdown
ARM CPU Specific Build Macros
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=============================
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Contents
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--------
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1. [Introduction](#1--introduction)
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2. [CPU Errata Workarounds](#2--cpu-errata-workarounds)
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3. [CPU Specific optimizations](#3--cpu-specific-optimizations)
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1. Introduction
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----------------
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This document describes the various build options present in the CPU specific
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operations framework to enable errata workarounds and to enable optimizations
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for a specific CPU on a platform.
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2. CPU Errata Workarounds
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--------------------------
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ARM Trusted Firmware exports a series of build flags which control the
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errata workarounds that are applied to each CPU by the reset handler. The
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errata details can be found in the CPU specific errata documents published
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by ARM:
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* [Cortex-A53 MPCore Software Developers Errata Notice][A53 Errata Notice]
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* [Cortex-A57 MPCore Software Developers Errata Notice][A57 Errata Notice]
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The errata workarounds are implemented for a particular revision or a set of
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processor revisions. This is checked by the reset handler at runtime. Each
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errata workaround is identified by its `ID` as specified in the processor's
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errata notice document. The format of the define used to enable/disable the
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errata workaround is `ERRATA_<Processor name>_<ID>`, where the `Processor name`
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is for example `A57` for the `Cortex_A57` CPU.
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All workarounds are disabled by default. The platform is responsible for
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enabling these workarounds according to its requirement by defining the
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errata workaround build flags in the platform specific makefile. In case
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these workarounds are enabled for the wrong CPU revision then the errata
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workaround is not applied. In the DEBUG build, this is indicated by
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printing a warning to the crash console.
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In the current implementation, a platform which has more than 1 variant
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with different revisions of a processor has no runtime mechanism available
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for it to specify which errata workarounds should be enabled or not.
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The value of the build flags are 0 by default, that is, disabled. Any other
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value will enable it.
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For Cortex-A53, following errata build flags are defined :
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* `ERRATA_A53_826319`: This applies errata 826319 workaround to Cortex-A53
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CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
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* `ERRATA_A53_836870`: This applies errata 836870 workaround to Cortex-A53
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CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
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r0p4 and onwards, this errata is enabled by default.
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For Cortex-A57, following errata build flags are defined :
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* `ERRATA_A57_806969`: This applies errata 806969 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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* `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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* `ERRATA_A57_826974`: This applies errata 826974 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
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* `ERRATA_A57_826977`: This applies errata 826977 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
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* `ERRATA_A57_828024`: This applies errata 828024 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
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* `ERRATA_A57_829520`: This applies errata 829520 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
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* `ERRATA_A57_833471`: This applies errata 833471 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
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3. CPU Specific optimizations
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------------------------------
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This section describes some of the optimizations allowed by the CPU micro
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architecture that can be enabled by the platform as desired.
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* `SKIP_A57_L1_FLUSH_PWR_DWN`: This flag enables an optimization in the
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Cortex-A57 cluster power down sequence by not flushing the Level 1 data
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cache. The L1 data cache and the L2 unified cache are inclusive. A flush
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of the L2 by set/way flushes any dirty lines from the L1 as well. This
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is a known safe deviation from the Cortex-A57 TRM defined power down
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sequence. Each Cortex-A57 based platform must make its own decision on
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whether to use the optimization.
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* `A53_DISABLE_NON_TEMPORAL_HINT`: This flag disables the cache non-temporal
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hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
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in a way most programmers expect, and will most probably result in a
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significant speed degradation to any code that employs them. The ARMv8-A
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architecture (see ARM DDI 0487A.h, section D3.4.3) allows cores to ignore
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the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
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flag enforces this behaviour. This needs to be enabled only for revisions
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<= r0p3 of the CPU and is enabled by default.
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* `A57_DISABLE_NON_TEMPORAL_HINT`: This flag has the same behaviour as
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`A53_DISABLE_NON_TEMPORAL_HINT` but for Cortex-A57. This needs to be
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enabled only for revisions <= r1p2 of the CPU and is enabled by default,
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as recommended in section "4.7 Non-Temporal Loads/Stores" of the
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[Cortex-A57 Software Optimization Guide][A57 SW Optimization Guide].
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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_Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved._
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[A57 SW Optimization Guide]: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
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[A53 Errata Notice]: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
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[A57 Errata Notice]: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf
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