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caa3e7e0a4
Move the data section to the common header.
I slightly tweaked some scripts as follows:
[1] bl1.ld.S has ALIGN(16). I added DATA_ALIGN macro, which is 1
by default, but overridden by bl1.ld.S. Currently, ALIGN(16)
of the .data section is redundant because commit 4128659076
("Fix boot failures on some builds linked with ld.lld.") padded
out the previous section to work around the issue of LLD version
<= 10.0. This will be fixed in the future release of LLVM, so
I am keeping the proper way to align LMA.
[2] bl1.ld.S and bl2_el3.ld.S define __DATA_RAM_{START,END}__ instead
of __DATA_{START,END}__. I put them out of the .data section.
[3] SORT_BY_ALIGNMENT() is missing tsp.ld.S, sp_min.ld.S, and
mediatek/mt6795/bl31.ld.S. This commit adds SORT_BY_ALIGNMENT()
for all images, so the symbol order in those three will change,
but I do not think it is a big deal.
Change-Id: I215bb23c319f045cd88e6f4e8ee2518c67f03692
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
119 lines
2.9 KiB
ArmAsm
119 lines
2.9 KiB
ArmAsm
/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <common/bl_common.ld.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
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OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(bl2u_entrypoint)
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MEMORY {
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RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
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}
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SECTIONS
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{
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. = BL2U_BASE;
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ASSERT(. == ALIGN(PAGE_SIZE),
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"BL2U_BASE address is not aligned on a page boundary.")
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#if SEPARATE_CODE_AND_RODATA
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.text . : {
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__TEXT_START__ = .;
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*bl2u_entrypoint.o(.text*)
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*(SORT_BY_ALIGNMENT(.text*))
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*(.vectors)
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. = ALIGN(PAGE_SIZE);
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__TEXT_END__ = .;
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} >RAM
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/* .ARM.extab and .ARM.exidx are only added because Clang need them */
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.ARM.extab . : {
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} >RAM
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.ARM.exidx . : {
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} >RAM
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.rodata . : {
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__RODATA_START__ = .;
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*(SORT_BY_ALIGNMENT(.rodata*))
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RODATA_COMMON
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. = ALIGN(PAGE_SIZE);
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__RODATA_END__ = .;
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} >RAM
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#else
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ro . : {
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__RO_START__ = .;
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*bl2u_entrypoint.o(.text*)
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*(SORT_BY_ALIGNMENT(.text*))
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*(SORT_BY_ALIGNMENT(.rodata*))
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RODATA_COMMON
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*(.vectors)
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__RO_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked as
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* read-only, executable. No RW data from the next section must
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* creep in. Ensure the rest of the current memory page is unused.
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*/
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. = ALIGN(PAGE_SIZE);
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__RO_END__ = .;
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} >RAM
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#endif
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/*
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* Define a linker symbol to mark start of the RW memory area for this
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* image.
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*/
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__RW_START__ = . ;
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DATA_SECTION >RAM
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STACK_SECTION >RAM
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BSS_SECTION >RAM
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XLAT_TABLE_SECTION >RAM
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#if USE_COHERENT_MEM
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/*
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* The base address of the coherent memory section must be page-aligned (4K)
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* to guarantee that the coherent data are stored on their own pages and
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* are not mixed with normal data. This is required to set up the correct
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* memory attributes for the coherent data page tables.
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*/
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coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
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__COHERENT_RAM_START__ = .;
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*(tzfw_coherent_mem)
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__COHERENT_RAM_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked
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* as device memory. No other unexpected data must creep in.
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* Ensure the rest of the current memory page is unused.
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*/
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. = ALIGN(PAGE_SIZE);
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__COHERENT_RAM_END__ = .;
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} >RAM
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#endif
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/*
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* Define a linker symbol to mark end of the RW memory area for this
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* image.
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*/
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__RW_END__ = .;
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__BL2U_END__ = .;
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__BSS_SIZE__ = SIZEOF(.bss);
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ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
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}
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